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Publications
Highlighted below are the MIND-related conference and journal papers authored by the
MIND research team for each the 10 research projects:
Project: Modeling and analysis of tunnel transistors with NEMO/OMEN
Principal investigator: Gerhard Klimeck - Purdue
2011
A. Paul, M. Luisier, and G. Klimeck,
"Influence of cross-section geometry and wire orientation on the phonon shifts in ultra-scaled Si nanowires,"
J. Appl. Phys., 110, 094308 (2011).
A. Paul, M. Luisier, and G. Klimeck,
"Shape and orientation effects on the ballistic phonon thermal properties of ultra-scaled Si nanowires,"
J. Appl. Phys., 110, 114309 (2011).
A. Paul and G. Klimeck,
"Strain effects on the phonon thermal properties of ultra-scaled Si nanowires,"
Appl. Phys. Lett., 99, 083115 (2011).
M. Luisier, T. Boykin, and G. Klimeck,
"Atomistic nanoelectronic device simulations with sustained performances up to 1.44 Pflop/s,"
ACP/IEEE Gordon Bell Prize Competition, Supercomputing, Nov. 2011, Seattle, WA.
A. Paul, K. Miao, G. Hegde, S. Mehrotra, M. Luisier, and G. Klimeck,
"Enhancement of thermoelectric efficiency by uniaxial tensile stress in n-type GaAs nanowires,"
IEEE Nano 2011, August 2011, Portland, OR.
A. Paul, G. Tettamanzi, S. Lee, S. Mehrotra, N. Collaert, S. Rogge, and G. Klimeck,
"Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs,"
J. Appl. Phys., 110, 121301 (2011).
S. Steiger, M. Povolotskyi, H.-H. Park, T. Kubis, and G. Klimeck,
"NEMO5: A parallel multiscale nanoelectronics modeling tool,"
IEEE Trans. Nanotechnology. vol. 10, pp. 1464-74 (2011).
S. Steiger, M. Salmani, D. Areshkin, A. Paul, T. Kubis, M. Povolotskyi, H.-H. Park, and G. Klimeck,
"Enhanced valence force field model for the lattice properties of galium arsenide,"
Phys. Rev. B., vol. 84, p. 155204 (2011).
G. C. Tettamanzi, A. Paul, S. Lee, S. R. Mehrotra, N. Collaert, S. Biesemans, G. Klimeck, and S. Rogge,
"Interface trap density metrology of state-of-the-art undoped Si N-FinFETs,"
IEEE Electron Device Lett., 32, 4, pp. 440-442, 2011.
S. G. Kim, A. Paul, M. Luisier, T. B. Boykin, G. Klimeck,
"Full 3D quantum transport simulation of atomistic interface roughness in silicon nanowire FETs,"
IEEE Trans. on Electron Devices, 58, 5 pp. 1371-1380, 2011.
2010
W.-S. Cho, M. Luisier, and G. Klimeck,
"Full-band simulations of band-to-band tunneling diodes,"
TECHCON, Sept. 2010, Austin, Texas.
S. Agarwal, G. Klimeck, and M. Luisier,
"Design ideas for leakage reduction in low power vertical tunneling field-effect transistors,"
IEEE Electron Device Lett., vol. 31, pp. 621-623, 2010.
T. Boykin, M. Luisier, M. Salmani-Jelodar, and G. Klimeck,
"Strain-induced, off-diagonal, same-atom parameters in empirical tight-binding theory suitable for [110] uniaxial strain applied to a silicon parameterization,"
Phys. Rev. B, 81, 125202, 2010.
M. Luisier and G. Klimeck,
"Simulation of nanowire tunneling transistors: From the Wentzel-Kramers-Brillouin approximation to full-band phonon-assisted tunneling,"
J. Appl. Phys., 107, 084507, 2010.
2009
M. Luisier and G. Klimeck,
“Performance comparisons of tunneling field-effect transistors made of InSb, carbon and GaSb-InAs broken gap heterostructures,”
International Electron Devices Meeting, Dec. 2009, Baltimore, MD.
M. Luisier and G. Klimeck,
“Investigation of InxGa1-xAs ultra-thin-body tunneling FETs using a full-band and atomistic approach,"
IEEE SISPAD, Dec. 2009, San Diego, CA.
M. Luisier and G. Klimeck,
“Atomistic full-band simulations of Si nanowire transistors with electron-phonon scattering,”
Phys. Rev. B, 80, 155430, 2009.
B. P. Haley, S. Lee, M. Luisier, G. Klimeck, H. Ryu F. Saied, S. Clark, and H. Bae,
“Advancing nanoelectronic device modeling through peta-scale computing and deployment on nanoHUB,”
Proc. SciDAC Conference, June 2009, San Diego, CA, J. Phys: Conf. Ser. vol. 180, 012075 (16pp) doi: 10.1088/1742-6596/180/1/012075.
M. Luisier and G. Klimeck,
“Atmostic, full-band design study of InAs band-to-band tunneling field-effect transistors,”
Electron Device Lett., 30, 6, 2009.
M. Luisier and G. Klimeck,
“Performance analysis of statistical samples of graphene nanoribbon tunneling transistors with line edge roughness,”
Appl. Phys. Lett., 94, 223505, 2009.
M. Luisier and G. Klimeck,
“Performance limitations of graphene nanoribbon tunneling FETS due to line edge roughness,”
Device Research Conf., June 2009, University Park, PA.
A. Paul, S. Mehrotra, G. Klimeck, and M. Luisier,
“On the validity of the top of the barrier quantum transport model for ballistic nanowire MOSFETs,”
IEEE Proc. 13th International Workshop on Computational Electronics, May 2009, Beijing, China.
S. Mehrotra, M. Luisier, and G Klimeck,
“Surface and orientation dependence on performance of trigated silicon nanowire pMOSFETs,”
Proc. 7th IEEE Workshop on Microelectronics and Electron Devices, Apr. 2009, Boise, ID.
2008
M. Luisier and G. Klimeck,
“A multi-level parallel simulation approach to electron transport in nano-scale transistors,”
Supercomputing 2008, Nov. 2008, Austin TX.
M. Luisier and G. Klimeck,
“Full-band and atomistic simulation of n- and p-doped double-gate MOSFETs for the 22 nm technology node,”
Int. Conf on Simulation of Semiconductor Processes and Devices, Sept. 2008, Hakone, Japan.
M. Luisier, N. Neophytou, N. Kharche, and G. Klimeck,
“Full-band and atomistic simulation of realistic 40 nm InAs HEMT,”
IEEE Int. Electron Devices Meeting, Dec. 2008, San Francisco, CA.
G. Klimeck and M. Luisier,
“From NEMO1D and NEMO3D to OMEN: Moving toward atomistic 3D quantum transport in nano-scale semiconductors,”
IEEE Int. Electron Devices Meeting, Dec. 2008, San Francisco, CA.
Project: Heterojunction p-n tunnel field-effect transistors (TFETs)
Principal investigators: Patrick Fay, Tom Kosel, Alan Seabaugh, Mark Wistey, Grace Xing - Notre Dame
2011
Q. Zhang, G. Zhou, H. Xing, A. Seabaugh, K. Xu, S. Hong, O. Kirillov, C. Richter, and N. Nguyen,
"Tunnel field-effect transistor heterojunction band alignment by internal photoemission spectroscopy,"
submitted, Appl. Phys. Lett.
R. Li, Y. Lu, G. Zhou, Q. Liu, S. D. Chae, T. Vasen, W. S. Hwang, Q. Zhang, P. Fay, T. Kosel, M. Wistey, H. Xing, and A. Seabaugh,
"AlGaSb/InAs tunnel field-effect transistor with on-current of 78 μA/μm at 0.5 V,"
submitted, IEEE Electron Device Lett.
Y. Lu, G. Zhou, R. Li, Q. Liu, Q. Zhang, T. Vasen, S. D. Chae, T. Kosel, M. Wistey, H. Xing, A. Seabaugh, and P. Fay,
"Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned,"
submitted, IEEE Electron Device Lett.
S. D. Chae, G. Zhou, I. Kwihangana, R. Li, Y. Lu, Q. Liu, T. Vasen, Q. Zhang, W.-S. Hwang, P. Fay, T. Kosel, M. Wistey, H. Xing, and A. Seabaugh,
"Characterization of interface traps in metal–high-k–InAs/GaSb TFETs,"
IEEE Semiconductor Interface Specialists Conference (SISC), Dec. 2011, Arlington, VA.
Q. Zhang, G. Zhou, H. Xing, A. Seabaugh, K. Xu, O. Kirillov, C. Richter, and N. Nguyen,
"Band alignment of TFET heterojunctions and post deposition annealing effects by internal photoemission spectroscopy,"
ISDRS, Dec. 2011, College Park, MD.
A. Seabaugh, S. D. Chae, P. Fay, W. S. Hwang, D. Jena, S. Hu, T. Kosel, S. Kurtz, R. Li, Q. Liu, Y. Lu, T. Vasen, M. Wistey, H. Xing, Q. Zhang, and G. Zhou,
"Fulfilling digital logic requirements by tunnel transistors,"
invited, 2nd Symposium for Energy Efficient Electronic Systems, Nov. 2011, Berkeley, CA.
R. Li, Y. Lu, S. D. Chae, G. Zhou, Q. Liu, C. Chen, M. S. Rahman, T. Vasen, Q. Zhang, P. Fay, T. Kosel, M. Wistey, H. Xing, S. Koswatta, and A. Seabaugh,
"InAs/AlGaSb heterojunction tunnel field-effect transistor with tunnelling in-line with the gate field,"
Physica Status Solidi C, 9, no. 2, pp. 389-392 (2012).
G. Zhou, Y. Lu, R. Li, Q. Zhang, W. S. Hwang, Q. Liu, T. Vasen, C. Chen, H. Zhu, J.-M. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. G. Xing.
"Vertical InGaAs/InP tunnel FETs with tunneling normal to the gate,"
IEEE Electron Dev. Lett., 32, 11, pp. 1516-18, 2011.
A. Seabaugh, S. D. Chae, P. Fay, W. S. Hwang, T. Kosel, R. Li, Q. Liu, Y. Lu, T. Vasen, M. Wistey, H. Xing, G. Zhou, and Q. Zhang,
"III-V tunnel field-effect transistors,"
invited, 220th ECS Meeting and Electrochemical Energy Summit, Oct. 2011, Boston, MA.
A. Seabaugh, S. D. Chae, P. Fay, W. S. Hwang, T. Kosel, R. Li, Q. Liu, Y. Lu, T. Vasen, M. Wistey, H. Xing, Q. Zhang, G. Zhou, and R. Wallace,
"Interface traps and low subthreshold swing in III-V tunnel FETs,"
invited, AVS Symposium, Oct. 2011, Nashville, TN.
A. Seabaugh,
"Fundamentals and current status of steep-slope tunnel field-effect transistors,"
invited, 41st European Solid-State Device Research Conference (ESSDERC), September 2011, Helsinki, Finland.
T. Vasen, Q. Liu, M. S. Rahman, G. Zhou, Y. Lu, R. Li, C. Chen, Q. Zhang, N. Goel, C. Park, J.-M. Kuo, H. Zhu, S. Koswatta, D. Wheeler, P. Fay, H. Xing, T. Kosel, M. Wistey, and A. Seabaugh,
"Lateral In0.53Ga0.47As Tunneling Field-Effect Transistor with regrown, self-aligned tunnel junction by Molecular Beam Epitaxy,"
TECHCON, Sept. 2011, Austin, TX.
G. Zhou, Y. Lu, R. Li, Q. Zhang, W. Hwang, Q. Liu, T. Vasen, H. Zhu, J. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing,
"Self-aligned InAs/Al0.45Ga0.55Sb vertical tunnel FETs,"
Device Research Conf., pp. 205-206 (2011).
G. Zhou, Y. Lu, R. Li, W. Hwang, Q. Zhang, Q. Liu, T. Vasen, H. Zhu, J. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing,
"Passivation effects of ALD oxides on self-aligned In0.53Ga0.47As/InAs/InP vertical tunnel FETs,"
Electronic Materials Conf., June 2011, Santa Barbara, CA.
A. Seabaugh, G. Bernstein, P. Fay, D. Jena, P. Kogge, T. Kosel, S. Hu, J. Nahas, M. Niemier, W. Porod, H. Xing, S. Datta, T. Mayer, V. Narayanan, G. Klimeck, and R. Wallace,
"Nanoelectronics Research Initiative,"
invited, International Nanotechnology Conference on Communication and Cooperation (INC7), May 2011, Albany, NY.
R. Li, Y. Lu, G. Zhou, Q. Liu, C. Chen, M. S. Rahman, T. Vasen, Q. Zhang, P. Fay, T. Kosel, M. Wistey, H. Xing, S. Koswatta, and A. Seabaugh,
"InAs/AlGaSb heterojunction tunnel FET with InAs airbridge drain,"
International Symposium on Compound Semiconductors (ISCS 2011) pp. 189-190.
G. Zhou, Y. Lu, R. Li, Q. Liu, P. Pinsukanjana, G. Wang, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing,
"Self-aligned In0.53Ga0.47As/InP vertical tunnel FET,"
CS Mantech, May 2011, Palm Springs, CA.
A. Seabaugh, P. Fay, T. Kosel, R. Li, Q. Liu, Y. Lu, T. Vasen, M. Wistey, H. Xing, Q. Zhang, and G. Zhou,
"III-V tunnel FETs,"
invited, WOCSEMMAD, February 2011, Savannah, GA.
2010
A. C. Seabaugh and Q. Zhang,
"Low-voltage tunnel transistors for beyond-CMOS logic,"
Proc. IEEE, vol. 98, 2095-2110, 2010.
S. O. Koswatta, S. J. Koester, and W. Haensch,
"On the possibility of obtaining MOSFET-like performance and sub-60 mV/decade swing in 1D broken-gap tunnel transistors,"
IEEE Trans. on Electron Devices, vol. 57, no. 12, 2010.
Q. Zhang, Y. Lu, H. Xing, S. Koester, and S. Koswatta,
"Scalability of atomic-thin-body (ATB) transistors based on graphene nanoribbons,"
IEEE Electron Device Letters, 31, 6, 2010.
G. Zhou, J. Zhu, P. Pinsukanjana, Y.-C. Kao, T. Kosel, P. Fay, M. Wistey, A. Seabaugh, and H. Xing,
"Regrown InGaAs tunnel junctions for TFETs,"
Electronic Materials Conf., June 2010, Notre Dame, IN.
Y. Lu, A. Seabaugh, P. Fay, S. J. Koester, S. E. Laux, W. Haensch, and S. O. Koswatta,
"Geometry dependent tunnel FET performance: Dilemma of electrostatics vs. quantum confinement,"
Device Research Conf., June 2010, Notre Dame, IN.
Y. Lu, A. Seabaugh, H. Xing, T. Kosel, S. Koswatta, J. Zhu, K Clark, J.-M. Kuo, P. Paul, and P. Fay,
"Effect of aluminum comparison on current-voltage characteristics of AlGaSb/InAs tunnel junction,"
Electronic Materials Conf., June 2010, Notre Dame, IN.
A. Seabaugh,
"Tunnel field-effect transistors - status and prospects,"
invited, Device Research Conf., June 2010, Notre Dame, IN.
A. Seabaugh,
"Narrow bandgap tunnel field-effect transistors for logic,"
invited, Int. Symp. Compound Sem., June 2010, Kagawa, Japan.
2009
S. Kabeer, T. Vasen, D. Wheeler, Q. Zhang, S. Koswatta, H. Zhu, K. Clark, J.-M. Kuo, Y.-C. Kao, S. Corcoran, B. Doyle, P. Fay,
T. Kosel, H. Xing, and A. Seabaugh,
“Effect of dopant profile on current-voltage characteristics of p+n+ In0.53Ga0.47As tunnel junctions,”
International Semiconductor Device Research Symposium, Dec. 2009, Baltimore, MD.
G. Zhou , S. Kabeer, D. Wheeler, A. Seabaugh, and H. G. Xing,
“Field modulation in heavily-doped thin-body p+InGaAs for tunnel FETs,”
International Semiconductor Device Research Symposium, Dec. 2009, Baltimore, MD.
D. Wheeler, S. Kabeer, Y. Lu, T. Vasen, Q. Zhang, G. Zhou, K. Clark, H. Zhu, Y.-C. Kao, P. Fay, T. Kosel, H. G. Xing, and
A. Seabaugh,
“Fabrication approach for lateral InGaAs tunnel transistors,”
International Semiconductor Device Research Symposium, Dec. 2009, Baltimore, MD.
S. O. Koswatta, S. J. Koester, and W. Haensch,
“1D broken-gap tunnel transistor with MOSET-like On-currents and sub-60mV/dec subthreshold swing,”
Int. Electron Devices Meeting, Dec. 2009, Baltimore, MD.
A. Seabaugh, D. Jena, T. Fang, P. Fay, S. Kabeer, T. Kosel, Y. Lu, S. Koswatta, K. Tahy, T. Vasen, D. Wheeler, H. Xing, Q. Zhang,
G. Zhou, J.-M. Kuo, P. Pinsukanjana, H. Zhu, and Y.-C. Kao,
“Low-subthreshold-swing tunnel transistors,”
Silicon Nanoelectronics Workshop, June 2009, Kyoto, Japan.
2008
Q. Zhang, S. Sutar, T. Kosel, and A. Seabaugh,
“Fully-depleted Ge interband tunnel transistor: Modeling and junction formation,”
Solid State Electronics, 53, 30-35, 2008.
Q. Zhang and A. Seabaugh,
“Can the interband tunnel FET outperform Si CMOS?,”
Device Research Conf., June 2008, Santa Barbara, CA.
Project: Heterojunction p-i-n tunnel transistor logic and architectures
Principal investigators: Suman Datta, Vijay Narayanan, Theresa Mayer - Penn State
2011
D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. Fastenau, D. Loubychev, A. Liu, and S. Datta
"Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered heterojunctions for 300mV logic applications,"
IEEE International Electron Devices Meeting, Dec. 2011, Washington DC.
L. Liu and S. Datta,
"Scaling length theory of double gate interband tunnel field-effect transistor,"
accepted, IEEE Trans. on Electron Dev.
V. Saripalli, S. Datta, V. Narayanan, Y. Xie, et al,
"Exploiting heterogeneity for energy efficiency in chip multiprocessors,"
accepted, IEEE J. Emerging and Selected Topics in Circuits and Systems.
D. K. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, and S. Datta,
"Experimental staggered source and N+ pocket (δ)-doped channel III-V tunnel FETs and their scalabilities,"
Applied Physics Express, vol. 4, pp. 024105, 2011.
E. Kultursay, S. Datta, and V. Narayanan,
"Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET CMP architectures,"
ISLPED 2011, Aug. 2011, Fukuoka, Japan.
V. Saripalli, A. Misra, S. Datta, and V. Narayanan,
"An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores,"
Design Automation Conference (DAC), June 2011, San Diego, CA.
Y. C. Chen, S. Soumya, G. Sun, Y. Xie, S. Datta, and V. Narayanan,
"Automated mapping for reconfigurable single electron transistor arrays,"
Design Automation Conference (DAC), June 2011, San Diego, CA.
D. Mohata, R. Bijesh, V. Saripalli, T. Mayer, and S. Datta,
"Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor,"
Device Research Conf., June 2011, Santa Barbara, CA.
V. Saripalli, S. Datta, J. Kulkarni (Intel), and V. Narayanan,
"Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design,"
NANOARCH 2011, June 2011, San Diego, CA.
2010
A. Ali, H. S. Madan, A. P. Kirk, R. M. Wallace, D. A. Zhao, D. A. Mourey, M. K. Hudait, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta,
"Fermi level unpinning of GaSb (100) using plasma enhanced atomic layer deposition of Al2O3 dielectric,"
Appl. Phys. Lett. 97,143502, 2010.
W. C. Kao, A. Ali, E. Hwang, S. Mookerjea, and S. Datta,
"Effect of interface states on sub-threshold response of III-V MOSFETs, MOS HEMTs and tunnel FETs,"
Solid-State Electronics, 54 (12), p. 1665, 2010.
V. Saripalli, L. Liu, S. Datta, and V. Narayanan,
"Energy-delay performance of nanoscale transistors exhibiting single electron behavior and associated logic circuits,"
J. of Low Power Electronics, vol. 6, no. 3, pp. Oct. 2010.
S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, and V. Narayanan,
"Non-silicon logic elements on silicon for extreme voltage scaling,"
invited, Proc. of the Silicon Nanoelectronics Workshop (SNW), pp.15-16, June 2010, Honolulu, Hawaii.
S. Datta,
"Compound semiconductor based tunnel transistor logic,"
invited, Lester Eastman Conference on High Performance Devices (LEC 2010), pp.178-179, Troy, NY, Aug. 2010.
A. Ali , H. Madan, S. Koveshnikov, S. Oktyabrsky, R. Kambhampati, T. Heeg, D. Schlom, and S. Datta,
"Small signal response of inversion layers in high mobility In0.53Ga0.47As MOSFETs made with thin high-k dielectrics,"
IEEE Trans. on Electron Devices, 57, 4, pp. 742-748, 2010.
S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta,
"Temperature dependent I-V characteristics of a vertical In0.53Ga0.47As tunnel FET (TFET),"
IEEE Electron Device Lett., 31, 6, 2010.
V. Saripalli, S. Datta, and N. Vijaykrishnan,
"Analyzing energy-delay behavior in room temperature single electron transistors,"
International Conference on VLSI Design, Jan. 2010, Bangalore, India.
L. Liu and S. Datta,
"Investigation of the scalability of ultra thin body double gate tunnel FET using physics based 2D analytical model,"
Device Research Conference, June 2010, Notre Dame, IN.
D. K. Mohata, D. Pawlik, L. Liu, S. Mookerjea, V. Saripalli, S. Rommel, and S. Datta,
"Implications of record peak current density In0.53Ga0.47As Esaki tunnel diode on tunnel FET logic applications,"
Device Research Conf., June 2010, Notre Dame, IN.
V. Saripalli, D. K. Mohata, S. Mookerjea, S. Datta, and V. Narayanan,
"Low power loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As tunnel FETs,"
Device Research Conf., June 2010, Notre Dame, IN.
D. Pawlik, S. Kurinec, S. Mookerjea, D. Mohata, S. Datta, S. Cohen, D. Ritter, and S. Rommel,
"Sub-micron InGaAs Esaki diodes with record high peak current density,"
Device Research Conf., June 2010, Notre Dame, IN.
J. Singh, R. Krishnan, S. Mookerjea, S. Datta, and V. Narayanan,
“A novel Si TFET based SRAM design for ultra low-power 0.3V VDD applications,”
15th Asia Pacific Design Automation Conf., Jan. 2010.
2009
S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallet, A. Ali, T. Mayer, V. Narayanan, D. Schlom, A. Liu, and S. Datta,
“Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications,”
late news paper, IEEE International Electron Devices Meeting, Dec. 2009.
H. Madan, A. Ali, S. Koveshnikov, and S. Datta,
“Interface state response in HfO2 gated strained InAs quantum-well FETs,”
40th IEEE Semiconductor Interface Specialists Conf., Dec. 2009.
W. C. Kao, E. Hwang, S. Mookerjea, and S. Datta,
“Impact of interface states on sub-threshold response of III-V MOSFETs, MOS HEMTs and tunnel FETs,”
40th IEEE Semiconductor Interface Specialists Conf., Dec. 2009.
A. Ali , H. Madan, S. Koveshnikov, S. Oktyabrsky, R. Kambhampati, T. Heeg, D. Schlom and S. Datta,
“Small signal response of inversion layers in high mobility In0.53Ga0.47As MOSFETs made with thin high-k dielectrics,”
ECS Trans., vol. 25, no. 6, pp. 271-284, “Physics and Technology of High-k Gate Dielectrics,” Oct. 2009.
A. Ali, H. Madan, S. Koveshnikov, and S. Datta,
“Small signal response of inversion layers in high mobility In0.53Ga0.47As MOSFETs made with thin high-k dielectrics,”
ECS Trans., Symposium on High Dielectric Constant Materials and Gate Stacks, Oct. 2009, Vienna, Austria.
V. Saripalli, V. Narayanan, and S. Datta,
“Ultra low energy binary decision diagram circuits using few electron transistors,”
Workshop on Nano-Bio Sensing Paradigms and Applications (in conjunction with Nano-Net 2009), Oct. 2009, Luzern, Switzerland.
S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan,
“On enhanced Miller capacitance effect in interband tunnel transistors,”
IEEE Electron Device Lett., 30, 10, 1102-1104, Oct. 2009.
S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan,
“Effective capacitance and drive current for tunnel-FET (TFET) CV/I estimation,”
IEEE Trans. Electron Devices, 56, 9, 2092-2098, Sept. 2009.
S. Mookerjea and S. Datta,
“Band-gap engineered hot carrier tunnel transistors,”
67th Device Research Conf. Digest, 121-122, June 2009, University Park, PA.
A. Ali, S. Mookerjea, E. Hwang, S. Koveshnikov, S. Oktyabrsky, V. Tokranov, M. Yakimov, R. Kambhampati, W. Tsai, and S. Datta,
“HfO2 gated, self aligned and directly contacted indium arsenide quantum-well transistors for logic applications: A temperature and bias dependent study,”
67th Device Research Conf. Digest, pp. 55-56, June 2009.
S. Mookerjea, R. Krishnan, A. Vallett, T. Mayer, and S. Datta,
"Inter-band tunnel transistor architecture using narrow gap semiconductors,"
ECS Trans., vol. 19, issue 5, pp. 287-292, "Graphene and Emerging Materials for Post-CMOS Applications", May 2009.
2008
V. Saripalli, S. Mookerjea, S. Datta, and V. Narayanan,
“Ultra low power signal processing architectures,”
Proc. IEEE Biomedical Circuits and Systems Conf., Nov. 2008, Baltimore, MD.
S. Eachempati, V. Saripalli, N. Vijaykrishan, and S. Datta,
“Reconfigurable BDD based quantum circuits,”
IEEE/ACM Int. Symp. on Nanoscale Architectures, June 2008, Anaheim, CA.
S. Mookerjea and S. Datta,
“Comparative study of Si, Ge, and InAs based steep subthreshold slope tunnel transistors for 0.25 V supply voltage logic applications,”
Device Research Conf., June 2008, Santa Barbara, CA.
Project: Nanofabrication platform for one-dimensional nanowire tunnel transistors
Principal investigators: Theresa Mayer, Suman Datta - Penn State
2011
B. D. Smith, T. S. Mayer, and C. D. Keating,
"Deterministic Assembly of Functional Nanostructures using Electric Fields,"
Annual Reviews of Physical Chemistry, in press.
T. S. Mayer, J. S. Mayer, and C. D. Keating,
"Electric-field Assisted Deterministic Assembly,"
Encyclopedia for Nanotechnology, in press.
2010
A. L. Vallett, S. Minassian, S. Datta, J. M. Redwing, and T. S. Mayer,
"Fabrication of axially doped silicon nanowire tunnel FETs and characterization of tunneling current,"
Device Research Conf., June 2010, Notre Dame, IN.
A. L. Vallett, S. Minassian, H. Liu, S. Datta, J. M. Redwing, and T. S. Mayer,
"Fabrication and characterization of axially doped silicon nanowire p-n junctions,"
Materials Research Society Spring Meeting, April 2010, San Francisco, CA.
A. L. Vallett, S. Minassian, P. Kaszuba, S. Datta, J. M. Redwing, and T. S. Mayer,
"Fabrication and characterization of axially doped silicon nanowire tunnel FETs,"
Nano Lett., 2010, 10 (12), pp. 4813-4818.
2009
T. J. Morrow, M. Li, J. Kim, T. S. Mayer, and C. D. Keating,
"Programmed assembly of DNA-coated nanowire devices,"
Science, 323, 352, 2009.
2008
T.-T. Ho, Y. Wang, S. Eichfeld, K.-K. Lew, B. Liu, S. Mohney, J. Redwing, and T. Mayer,
“In situ axially-doped n-channel silicon nanowire field effect transistors,”
Nano Letters, 8(12), pp. 4359-4364, 2008.
A. Vallet, S. Eichfeld, J. Redwing, T. Mayer, A. Deering, R. Wells, and P. Kaszuba,
“Junction delineation of in-situ doped silicon nanowires by scanning Kelvin probe microscopy,”
Fall Materials Research Society Meeting, Dec. 2008, Boston, MA.
Project: Characterization of tunnel field-effect transistor (TFET) interfaces (new project in 2011)
Principal investigators: Robert Wallace, Jiyoung Kim - University of Texas at Dallas
2011
B. Brennan, H. Dong, D. Zhernokletov, J. Kim, and R. M. Wallace,
"Surface and interface reaction study of half cycle atomic layer deposited Al2O3 on chemically treated InP surfaces,"
Appl. Phys. Exp., 4, 125701, 2011.
D. Zhernokletov, H. Dong, B. Brennan, J. Kim, and R. M. Wallace,
"Half-cycle atomic layer deposition studies of HfO2 on the GaSb(001) surface,"
AVS 58th International Symposium, Oct. 2011, Nashville, TN
A. Seabaugh, S. D. Chae, P. Fay, W. S. Hwang, T. Kosel, R. Li, Q. Liu, Y. Lu, T. Vasen, M. Wistey, H. Xing, Q. Zhang, G. Zhou, and R. Wallace,
"Interface traps and low subthreshold swing in III-V tunnel FETs,"
invited, AVS Symposium, Oct. 2011, Nashville, TN.
M. Milojevic, R. Contreras-Guerrero, E. O'Connor, B. Brennan, P. K. Hurley, J. Kim, C. L. Hinkle, and R. M. Wallace,
"In-situ characterization of Ga2O passivatin of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition,"
Appl. Phys. Lett., 99, 042904, 2011.
S. McDonnell, D. M. Zhernokletov, A. P. Kirk, J. Kim, and R. M. Wallace,
"In situ x-ray photoelectron spectroscopy characterization of Al2O3/GaSb interface evolution,"
Applied Surface Science, 257, pp. 8747-8751, 2011.
Project: Graphene nanoribbon tunnel field-effect transistors (GNR TFETs)
Principal investigators: Debdeep Jena, Grace Xing - Notre Dame
2012
W. S. Hwang, K. Tahy, P. Zhao, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy, Jr., D. K. Gaskill, H. Xing, A. C. Seabaugh, and D. Jena,
"Wafer-scale graphene nanoribbons for tunnel FET applications,"
submitted, 19th Korean Conference on Semiconductors, Feb. 2012, Seoul, Korea.
2011
W. S. Hwang, K. Tahy, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D. K. Gaskill, H. Xing, A. C. Seabaugh, and D. Jena,
"Fabrication of top-gated epitaxial graphene nano-ribbon FETs using hydrogen silsesquioxane (HSQ),"
submitted, J. Vacuum Science and Technology.
B. Sensale-Rodriguez, T. Fang, R. Yan, M. Kelly, D. Jena, L. Liu, and H. Xing,
"Unique prospects for graphene-based terahertz modulators,"
Appl. Phys. Lett. 99, 113104 (2011).
A. Liao, J. Wu, X. Wang, K. Tahy, D. Jena, H. Dai, and E. Pop,
"Thermally-limited current carrying ability of graphene nanoribbons,"
TECHCON, Sept. 2011, Austin, TX.
K. Tahy, W. S. Hwang, J. L. Tedesco, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D.K. Gaskill, H. Xing, A. C. Seabaugh,
and D. Jena,
"Large scale fabrication of sub-10 nm graphene nanoribbon field effect transistors,"
TECHCON, Sept. 2011, Austin, TX.
B. Gao, G. Hartland, T. Fang, M. Kelly, D. Jena, H. Xing, and L. Huang,
"Studies of intrinsic hot phonon dynamics in suspended graphene by transient absorption microscopy,"
Nano Lett., 2011, 11 (8), pp 3184–3189.
P. Zhao, Q. Zhang, D. Jena, and S. Koswatta,
"Influence of metal-graphene contacts on the operation and scalability of graphene field-effect transistors,"
IEEE Trans. Electron Dev., 58, 9, pp. 3170-3178, 2011.
L. Huang, B. Gao, G. Hartland, M. Kelly, H. Xing,
"Ultrafast relaxation of hot optical phonons in monolayer and multilayer graphene on different substrates,"
Surface Science, 605, 17-18, pp. 1657-1661, 2011.
W. S. Hwang, K. Tahy, J. L. Tedesco, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D. K. Gaskill, H. Xing, A. C. Seabaugh,
and D. Jena,
"Fabrication of top-gated sub-10 nm epitaxial graphene nanoribbon FETs using hydrogen silsesquioxane (HSQ),"
Electronic Materials Conf., June 2011, Santa Barbara, CA.
K. Tahy, W. S. Hwang, J. L. Tedesco, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D. K. Gaskill, H. Xing, A. C. Seabaugh, and D. Jena,
"Sub-10 nm epitaxial graphene nanoribbon FETs,"
IEEE Device Research Conf., Tech. Digest, June 2011.
P. Zhao, D. Jena, and S. Koswatta,
"RF performance projections for 2D graphene transistors: Role of parasitics at the ballistic transport limit,"
IEEE Device Research Conf., Tech. Digest, June 2011.
K. Tahy, W. S. Hwang, J. L. Tedesco, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D. K. Gaskill, H. Xing, A. C. Seabaugh,
and D. Jena,
"Control of the unintentional doping in epitaxial graphene FETs,"
Graphene 2011, April 2011, Bilbao, Spain.
D. Jena, K. Tahy, T. Fang, P. Zhao, W. S. Hwang, M. Kelly, S. Koswatta, K. Gaskill, R. L. Myers-Ward, J. Tedesco, C. Eddy, R. Li, H. Xing, and A. Seabaugh,
"Graphene transistors for digital applications"
The Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2011, Orlando, FL.
2010
A. Konar, T. Fang, and D. Jena,
"Effect of high-k gate dielectrics on charge transport in graphene-based field effect transistors,"
Phys. Rev. B., 82, 115452 (2010).
L. Huang, G. Hartland, L.-Q. Chu, Luxmi, R. Feenstra, C. Lian, K. Tahy, and H. Xing,
"Ultrafast transient absorption microscopy studies of carrier dynamics in epitaxial graphene,"
Nano Lett., 10, 1308, 2010.
C. Lian, K. Tahy, T. Fang, G. Li, H. Xing, and D. Jena,
"Quantum transport in graphene nanoribbons patterned by metal masks,"
Appl. Phys. Lett., 96, 103109, 2010.
K. Tahy, M. J. Fleming, B. Raynal, V. Protasenko, S. Koswatta, D. Jena, H. Xing, and M. Kelly,
"Device characteristics of single-layer graphene FETs grown on copper,"
Device Research Conf., June 2010, Notre Dame, IN.
N. Sun, K. Tahy, J. L. Tedesco, R. L. Myers-Ward, P. M. Campbell, C. R. Eddy Jr., D. K. Gaskill, H. Xing, D. Jena, and S. T. Ruggiero,
"Electrical noise in exfoliated and epitaxial graphene,"
Electronic Materials Conf., June 2010, Notre Dame, IN.
K. Tahy, H. Xing, and D. Jena,
"Graphene nanoribbon p-n junction FETs: Experimental results and modeling,"
IEEE Les Eastman Conf., Aug. 2010, Troy, NY.
T. Fang, A.Konar, H. Xing, and D. Jena,
"Carrier transport in 2D graphene p-n junctions,"
Electronic Materials Conf., June 2010, Notre Dame, IN.
M. Kelly, K. Tahy, M.J. Fleming, B. Raynal, V. Protasenko, D. Jena, and H. Xing,
"Fabrication and characterization of graphene materials via CVD on copper based substrates,"
Electronic Materials Conf., June 2010, Notre Dame, IN.
2009
D. Jena, K. Tahy, A. Konar, T. Fang, Q. Zhang, S. Koswatta, H. Xing, and A. Seabaugh,
“Graphene electronics,”
8th Topical Workshop on Heterostructure Microelectronics (TWHM),
Aug. 2009, Nagano, Japan.
D. Jena, K. Tahy, A. Konar, T. Fang, Q. Zhang, S. Koswatta, H. Xing, and A. Seabaugh,
“Graphene based transistors,”
18th European Workshop on Heterostructure Technology (HETECH), Nov. 2009, Ulm, Germany.
C. Lian, K. Tahy, T. Fang, G. Li, H. Xing, and D. Jena,
“Quantum transport in patterned graphene nanoribbons,”
International Semiconductor Device Research Symposium (ISDRS), Dec. 2009, Baltimore, MD.
K. Tahy, C. Lian, H. Xing, and D. Jena,
“Operation regimes of double-gated graphene nanoribbon FETs,”
International Semiconductor Device Research Symposium (ISDRS), Dec. 2009, Baltimore, MD.
D. Jena,
“A theory for the high-field current-carrying capacity of 1D semiconductors,”
J. Appl. Phys., 105, 123701, 2009.
K. Tahy, D. Shilling, T. Zimmermann, H. Xing, P. Fay, Luxmi, R. Feenstra, and D. Jena,
“Gigahertz operation of epitaxial graphene transistors,”
Device Research Conf., June 2009, University Park, PA.
K. Tahy, S. Koswatta, T. Fang, Q. Zhang, H. Xing, and D. Jena,
“High-field transport properties of 2D and nanoribbon graphene FETs,”
Device Research Conf., June 2009, University Park, PA.
2008
Q. Zhang, T. Fang, H. Xing, A. Seabaugh, and D. Jena,
“Graphene nanoribbon tunnel transistors,”
IEEE Electron Device Lett., 29, 1344-1346, 2008.
T. Fang, A. Konar, H. Xing, and D. Jena,
“Mobility in semiconducting graphene nanoribbons: Phonon, impurity, and edge roughness scattering,”
Phys. Rev. B, 78, 205403, 2008.
X. Luo, Y. Lee, A. Konar, T. Fang, G. Xing, G. Snider, and D. Jena,
“Current-carrying capacity of long and short channel 2D graphene transistors,”
Device Research Conf., June 2008, Santa Barbara, CA.
D. Jena, T. Fang, Q. Zhang, and G. Xing,
“Zener tunneling in semiconducting nanotube and graphene nanoribbon p-n junctions,”
Appl. Phys. Lett., 93, 112106, 2008.
T. Fang, A. Konar, G. Xing, and D. Jena,
“Carrier statistics and quantum capacitance of graphene sheets and ribbons,”
Appl. Phys. Lett., 91, 092109, 2007.
Project: Applications and architectures for nanomagnet logic (NML)
Principal investigators: György Csaba, X. Sharon Hu, Peter Kogge, Michael Niemier, Wolfgang Porod - Notre Dame
2012
X. Ju, S. Wartenburg, J. Rezgani, M. Becherer, J. Kiermaier, S. Brietkreutz, D. Schmitt-Landsiedel, W. Porod, P. Lugli, and G. Csaba,
"Nanomagnet logic from partially irradiated Co/Pt nanomagnets,"
IEEE Trans. Nanotechnology. 11, 1, pp. 97-104, 2012.
2011
G. Csaba, M. Becherer, and W. Porod,
"Development of CAD tools for nanomagnet logic devices,"
submitted, International J. of Circuit Theory and Applications.
G. Csaba, J. Kiermaier, M. Becherer, S. Breitkreutz, X. Ju, P. Lugli, D. Schmitt-Landsiedel, and W. Porod,
"Clocking magnetic field-coupled devices by domain walls,"
accepted, J. Appl. Phys.
E. Varga, G. Csaba, A. Imre, and W. Porod,
"Simulation of magnetization reversal and domain-wall trapping in submicron permalloy wires and different wire geometries,"
accepted, IEEE Trans. Nanotechnology
M. Ottavi, et al, P. Kogge,
"Partially reversible pipelined QCA circuits: Combining low power with high throughput,"
IEEE Trans. Nanotechnology., 10, 6, pp. 1383-1393, 2011.
E. Varga, G. Csaba, G. H. Bernstein, and W. Porod,
"Implementation of a nanomagnetic full adder circuit,"
IEEE NANO, Aug. 2011, Portland, OR.
M. Crocker, M. T. Niemier, and X. S. Hu,
“A reconfigurable PLA architecture for nanomagnet logic,”
ACM Journal of Emerging Technology and Computing Systems, accepted, ACM Journal on Emerging Technologies in Computing, 2011.
2010
A. Dingler, M. T. Niemier, X. S. Hu, and E. Lent,
"Performance and energy impact on locally controlled NML circuits,"
ACM Journal on Emerging Technologies in Computing Systems, 7(1), p. 1-24, 2010.
M. Crocker, X. S. Hu, and M. Niemier,
"Design and comparison of NML systolic architectures,"
Proc. of IEEE/ACM International Symposium on Nanoscale Architectures, p. 29-34, June 2010, Anaheim, CA.
2009
M. Crocker, X. S. Hu, and M. T. Niemier,
“Defects and faults in QCA-based PLAs,”
ACM Journal of Emerging Technology and Computing Systems, Vol. 5, No. 2, p. 1-27, 2009.
A. Dingler, M. Niemier, S. Hu, M. Alam, and M. Garrison,
“System-level energy and performance projections for nanomagnet-based logic,”
Proc. IEEE Symposium on Nanoscale Architectures, p. 21-26, July 2009, San Francisco, CA.
2008
M. Crocker, X. Sharon Hu, M. Niemier, M. Yan, and G. Bernstein,
“PLAs in quantum-dot cellular automata,”
IEEE Transactions on Nanotechnology, vol. 7, no.3, pp.376-386, May 2008.
S. Hu and M. Niemier,
“Computing with nearest neighbor interactions: A nanomagnetic implementation,”
invited, Proc. 6th IEEE/ACM/IFIP Int. Conf. on Hardware/Software Codesign and System Synthesis, Oct. 2008, pp. 223-330, Atlanta, GA.
M. Niemier, M. Crocker, and S. Hu,
“Fabrication variations and defect tolerance for nanomagnet-based QCA,”
23rd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, p. 534-542, Oct. 2008, Cambridge, MA.
M. Niemier, A. Dingler, S. Hu, M. Alam, G. Bernstein, and W. Porod,
“Bridging the gap between nanomagnetic devices and circuits,”
26th IEEE Int. Conf. on Computer Design, Oct. 2008, pp. 506-513, Lake Tahoe, CA.
Project: Designs and prototypes of nanomagnet logic (NML) circuits with reduced energy, latency, and area
Principal investigators: Gary Bernstein, György Csaba, Sharon Hu, Joe Nahas, Mike Niemier, Wolfgang Porod - Notre Dame
2012
A. Dingler, S. Kurtz, M. Niemier, X. S. Hu, G. Csaba, J. Nahas, W. Porod, G. Bernstein, P. Li, and V. K. Sankar,
"Making non-volatile nanaomagnet logic non-volatile,"
submitted, Design Automation Conference.
2011
S. Liu, X. S. Hu, J. Nahas, M. Niemier, G. H. Bernstein, and W. Porod,
“Exploring the design of magnetic-electrical interface for nanomagnet logic,”
TECHCON, Sept. 2011, Austin, TX.
S. Liu, X. S. Hu, J. J. Nahas, M. Niemier, W. Porod, and G. H. Bernstein,
"Magnetic-electrical interface for nanomagnet logic,"
IEEE Trans. on Nanotechnology, 10, 4, pp. 757-763, 2011.
S. Kurtz, E. Varga, M. Niemier, W. Porod, G. H. Bernstein, and X. S. Hu,
"Two input, non-majority magnetic logic gates: Experimental demonstration and future prospects,"
invited, J. of Physics: Condensed Matter, 23(5), p. 053202, 2011.
S. Liu, X. S. Hu, J. Nahas, and M. T. Niemier,
"Design and optimization of magnetic-electrical interfaces for NML circuit output,"
Work in Progress session, 2011 Design Automation Conference, June 2011, San Diego, CA.
2010
E. Varga, M. Siddiq, M. T. Niemier, G. H. Bernstein, and W. Porod,
"Experimental investigation of slanted supermalloy nanomagnets and their application in nanomagnet logic,"
TECHCON, Sept. 2010, Austin, Texas.
M. Alam, G. H. Bernstein, J. Bokor, D. Carlton, X. S. Hu, S. Kurtz, B. Lambson, M. T. Niemier, W. Porod, M. Siddiq, and E. Varga,
"Experimental progress of and prospects for nanomagnet logic (NML),"
2010 Symposia on VLSI Technology and Circuits, June 2010, Honolulu, HI.
E. Varga, S. Liu, M. T. Niemier, W. Porod, X. S. Hu, G. H. Bernstein, and A. Orlov,
"Experimental demonstration of fanout for nanomagnet logic,"
Proc. of the Device Research Conference, p. 95-96, 2010.
E. Varga, M. T. Niemier, G. H. Bernstein, W. Porod, and X. S. Hu,
"Programmable nanomagnet-logic majority gate,"
Proc. of the Device Research Conference, p. 85-86, 2010.
E. Varga, M. Siddiq, M. T. Niemier, M. T. Alam, G. H. Bernstein, W. Porod, X. S. Hu, and A. Orlov,
"Experimental demonstration of non-majority, nanomagnet logic gates,"
Proc. of the Device Research Conference, p. 87-88, 2010.
E. Varga, A. Orlov, M. T. Niemier, X. S. Hu, G. H. Bernstein, and W. Porod,
"Experimental demonstration of fanout for nanomagnet logic,"
IEEE Trans. on Nanotechnology, 9(6), p. 668-670, 2010.
2009
A. Dingler, M. J. Siddiq, M. T. Niemier, X. Sharon Hu, M. T. Alam, G. H. Bernstein, and W. Porod,
“Controlling magnet circuits: How clock structure implementation will impact power and correctness,”
IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, p. 94-102, Oct. 2009, Chicago, IL.
E. Varga, M. Niemier, G. Bernstein, W. Porod, and S. Hu,
“Non-volatile and reprogrammable MCQA-based majority gates,”
Proc. Device Research Conf., June 2009, University Park, PA.
2008
M. Niemier, A. Dingler, and S. Hu,
“Design tradeoffs for improved performance in MQCA-based systems,”
1st IEEE Int. Workshop on Design and Test of Nano Devices, Circuits and Systems, Sept. 2008, pp. 35-38, Cambridge, MA.
Project: Design and fabrication of energy efficient clocks for nanomagnet logic (NML)
Principal investigators: Gary Bernstein, X. Sharon Hu, Joe Nahas, Michael Niemier, Wolfgang Porod - Notre Dame
2011
P. Li, G. Csaba, V. K. Sankar, X. Ju, P. Lugli, X. S. Hu, M. Niemier, W. Porod, and G. H. Bernstein,
"Switching behavior of lithographically fabricated nanomagnets for logic applications,"
accepted, J. Appl. Phys.
P. Li, G. Csaba, V. K. Sankar, X. S. Hu, M. Niemier, W. Porod, and G. H. Bernstein,
“Switching behavior of lithographically fabricated nanomagnets for logic applications,”
Conference on Magnetism and Magnetic Materials (MMM), Oct. 2011, Scottsdale, AZ.
M. T. Niemier, G. H. Bernstein, A. Dingler, X. S. Hu, S. Kurtz, S. Liu, J. Nahas, W. Porod, M. Siddiq, and E. Varga,
"Nanomagnet logic: Progress toward system-level integration,"
invited, J. of Physics: Condensed Matter., 23, 493202, 2011.
M. T. Alam, S. Kurtz, M. J. Siddiq, M. T. Niemier, G. H. Bernstein, X. S. Hu, and W. Porod,
"On-chip clocking of nanomagnet logic lines and gates,"
IEEE Trans. Nanotechnology, DOI: 10.1109/TNANO.2011.2169983.
2010
M. T. Alam, M. J. Siddiq, G. H. Bernstein, M. Niemier, W. Porod, and X. S. Hu,
“On-chip clocking for nanomagnet logic devices,”
IEEE Trans. on Nanotechnology, vol. 9(3), p. 348-351, 2010.
2009
M. Alam, M. Siddiq, M. Niemier, X. S. Hu, W. Porod, and G. Bernstein,
“Fabrication of on-chip clock structure for nanomagnet QCA (MQCA),”
TECHCON, Sept. 2009, Austin, TX.
Project: Architectures and benchmarking for tunnel field-effect transistors (TFETs) and nanomagnet logic (NML)
Principal investigators: X. Sharon Hu, Peter Kogge, Joe Nahas, Michael Niemier, Wolfgang Porod, Alan Seabaugh - Notre Dame
2010
K. Bernstein, R. Cavin, W. Porod, A. Seabaugh, and J. Welser,
"Device and architecture outlook for beyond-CMOS switches,"
Proc. IEEE, vol. 98, no. 2, pp. 2169-2184 (2010).
A. Seabaugh,
"Emerging energy-efficient device technologies vs. ultimate CMOS,"
University Governent Industry Micro-Nano Symposium, June 2010, West Lafayette, IN.
2009
W. Porod et al.,
“Nanomagnetic logic,”
invited, 1st Berkeley Symposium on Energy-Efficient Systems, June 2009, Berkeley, CA.
2008
M. Alam, S. Kurtz, M. Niemier, S. Hu, G. Bernstein, and W. Porod,
“Magnetic logic based on coupled nanomagnets: Clocking structures and power analysis,”
invited, IEEE NANO 2008, Aug. 2008, Arlington, TX.
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