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Conference and journal papers authored by the MIND research team.

Lateral field-effect tunnel transistors (Notre Dame)

Q. Zhang, S. Sutar, T. Kosel, and A. Seabaugh, “Fully-depleted Ge interband tunnel transistor: Modeling and junction formation,” Solid State Electronics, 53, 30-35, 2008. [pdf]

Q. Zhang, T. Fang, H. Xing, A. Seabaugh, and D. Jena, “Graphene nanoribbon tunnel transistors,” IEEE Electron Device Lett., 29, 1344-1346, 2008. [pdf]

Q. Zhang and A. Seabaugh, “Can the interband tunnel FET outperform Si CMOS?,” Device Research Conf., June 2008, Santa Barbara, CA. [pdf]

Vertical heterostructure tunnel transistors (Penn State/Cornell)

V. Saripalli, S. Mookerjea, S. Datta, and V. Narayanan, “Ultra low power signal processing architectures,” Proc. IEEE Biomedical Circuits and Systems Conf., Nov. 2008, Baltimore, MD. [pdf]

S. Eachempati, V. Saripalli, N. Vijaykrishan, and S. Datta, “Reconfigurable BDD based quantum circuits,” IEEE/ACM Int. Symp. on Nanoscale Architectures, June 2008, Anaheim, CA. [pdf]

S. Mookerjea and S. Datta, “Comparative study of Si, Ge, and InAs based steep subthreshold slope tunnel transistors for 0.25 V supply voltage logic applications,” Device Research Conf., June 2008, Santa Barbara, CA. [pdf]

1-D nanowire tunnel transistors (Penn State)

T. J. Morrow, M. Li, J. Kim, T. S. Mayer, and C. D. Keating, "Programmed assembly of DNA-coated nanowire devices," Science, 323, 352, 2009. [pdf]

Thermal management and logic circuits (Purdue/Georgia Tech)

L. Weng, L. Zhang, Y. P. Chen, and L. P. Rokhinson, “Atomic force microscope local oxidation nanolithography of graphene,” Appl. Phys. Lett., 93, 093107, 2008. [pdf]

Q. Yu, J. Lian, S. Siriponglert, H. Li, Y. P. Chen, and S.-S. Pei, “Graphene segregated on Ni surfaces and transferred to insulators,” Appl. Phys. Lett., 93, 113103, 2008. [pdf]

Epitaxial spin FETs on Si (Purdue/Univ. Texas-Dallas)

T. Shen, Y. Q. Wu, M. A. Capano, L. P. Rokhinson, L. W. Engel, and P. D. Ye, “Magnetoconductance oscillations in graphene antidot arrays,” Appl Phys. Lett., 93, 122102, 2008. [pdf]

Extremely-scaled gated tunnel transistors (Notre Dame)

T. Fang, A. Konar, H. Xing, and D. Jena, “Mobility in semiconducting graphene nanoribbons: Phonon, impurity, and edge roughness scattering,” Phys. Rev. B, 78, 205403, 2008. [pdf]

X. Luo, Y. Lee, A. Konar, T. Fang, G. Xing, G. Snider, and D. Jena, “Current-carrying capacity of long and short channel 2D graphene transistors,” Device Research Conf., June 2008, Santa Barbara, CA. [pdf]

D. Jena, T. Fang, Q. Zhang, and G. Xing, “Zener tunneling in semiconducting nanotube and graphene nanoribbon p-n junctions,” Appl. Phys. Lett., 93, 112106, 2008. [pdf]

T. Fang, A. Konar, G. Xing, and D. Jena, “Carrier Statistics and Quantum Capacitance of Graphene Sheets and Ribbons,” Appl. Phys. Lett., 91, 092109, 2007. [pdf]

Energy dissipation in nonequilibrium systems (Illinois)

A. Liao, Y. Zhao, and E. Pop, "Avalanche-induced current enhancement in semiconducting carbon nanotubes," Phys. Rev. Lett., 101, 256804, 2008. [pdf]

E. Pop, “The role of electrical and thermal contact resistance for Joule breakdown of single-wall carbon nanotubes,” Nanotechnology, 19, 295202, 2008. [pdf]

A. Liao and E. Pop, “Impact ionization in semiconducting single-wall carbon nanotubes,” Device Research Conf., June 2008, Santa Barbara, CA. [pdf]

3-D quantum transport modeling (Purdue)

M. Luisier, N. Neophytou, N. Kharche, and G. Klimeck, “Full-band and atomistic simulation of realistic 40nm InAs HEMT,” IEEE Int. Electron Devices Meeting, Dec. 2008, San Francisco, CA. [pdf]

G. Klimeck and M. Luisier, “From NEMO1D and NEMO3D to OMEN: Moving toward atomistic 3D quantum transport in nano-scale semiconductors,” IEEE Int. Electron Devices Meeting, Dec. 2008, San Francisco, CA. [pdf]

Nanomagnet logic devices (Notre Dame)

M. Niemier, M. Crocker, and S. Hu, “Fabrication variations and defect tolerance for nanomagnet-based QCA,” 23rd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, Oct. 2008, Cambridge, MA. [pdf]

M. Niemier, A. Dingler, S. Hu, M. Alam, G. Bernstein, and W. Porod, “Bridging the gap between nanomagnetic devices and circuits,” 26th IEEE Int. Conf. on Computer Design, Oct. 2008, pp. 506-513, Lake Tahoe, CA. [pdf]

M. Niemier, A. Dingler, and S. Hu, “Design tradeoffs for improved performance in MQCA-based systems,” 1st IEEE Int. Workshop on Design and Test of Nano Devices, Circuits and Systems, Sept. 2008, pp. 35-38, Cambridge, MA. [pdf]

M. Crocker, S. Hu, and M. Niemier, “Defect tolerance in QCA-based PLAs,” IEEE/ACM Int. Symp. on Nanoscale Architectures, June 2008, pp. 46-53, Anaheim, CA. [pdf]

Architectures for emerging NRI devices (Notre Dame)

M. Alam, S. Kurtz, M. Niemier, S. Hu, G. Bernstein, and W. Porod, “Magnetic logic based on coupled nanomagnets: Clocking structures and power analysis,” invited paper, IEEE NANO 2008, Aug. 2008, Arlington, TX. [pdf]