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These scripts / files have been developed by Praveen Kalla,
University of Notre Dame, while working at NEC Laboratories
Inc. They are all covered by copyright laws pertaining to 
both institutions. They can be used for acadameic purposes
for free of cost, but not for commercial purposes.

The author does not assume any kind of responsibility for 
any damage through the use of these scripts / programs.

Some files might have been modified from their original form
as available at SUN Microsystems website. These files would
be covered under the copyright laws of SUN Microsystems as well

author contact 	: nkalla@cse.nd.edu (www.nd.edu/~nkalla)
advisors 	: Dr. Sharon Hu (www.nd.edu/~shu)
		: Dr. Joerg Henkel (henkel@nec-labs.com)

Do not remove this information from these files.

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=================================================================

Aug 1st : 2001 :

	Procedure for working with Sente :

	0. Create a file which contains the list of verilog files.
		- sparc_files
	1. Create sente/. Start sente 
	2. Create scenario, specify startup file, compile
	3. Open sys.v ( module testbench)
	4. 	Add $sente_init call. 	Specify the sente.opt path
	5. In the sente.opt :	add
		-iaf <path_to_output_activityfile>
	6. In modelsim.ini : add/edit to [vsim] section
		Veriuser <pli1.so> <pli2.so> ... 
	6.5: See that appropriate prog.dat exists. (the program image)
	7. Start modelsim and run the macro sente_run.do.
		collects data for sente power estimator.
	8. Start sente and start power wizard.
		estimates the power consumption.

	Refer to Sente manuals for further detailed information on each
	of these steps.