/* ----------------------------------------------------- */ These scripts / files have been developed by Praveen Kalla, University of Notre Dame, while working at NEC Laboratories Inc. They are all covered by copyright laws pertaining to both institutions. They can be used for acadameic purposes for free of cost, but not for commercial purposes. The author does not assume any kind of responsibility for any damage through the use of these scripts / programs. Some files might have been modified from their original form as available at SUN Microsystems website. These files would be covered under the copyright laws of SUN Microsystems as well author contact : nkalla@cse.nd.edu (www.nd.edu/~nkalla) advisors : Dr. Sharon Hu (www.nd.edu/~shu) : Dr. Joerg Henkel (henkel@nec-labs.com) Do not remove this information from these files. /* ----------------------------------------------------- */ Here I have outlined the procedure which was used to construct the power models for the MicroSparc IIep. Similar flow can be used for constructing models for other cores, but efforts will vary depending upon the tools available. Terminology : ---------------------------------------------------------------------------------- Core : VHDL / Verilog description of a microprocessor core. search : This readme was written using Vi. So no proper cross-references have been provided. However, wherever possible, "search for abc-xyz" has been given. Hopefully doing a search for abc-xyz should take the reader to all related items. Sources : wherever this is mentioned it implies that the corresponding files should be found on the website. Basic requirements: ---------------------------------------------------------------------------------- Core : VHDL/ Verilog description of Core (MicroSparcIIep) Gate-level simulator : ModelSim Power estimator : Sente (Wattwatcher / Peakwatcher) from Sequence Design Inc. (gate-level estimator) Compiler / Assembler / Linker : The toolkit provided by Sparc does not work. So I used those provided for Leon (gaisler.com) Knowledge required : VHDL, verilog, verilog-PLI, C, use of ModelSim, Sente, Tcl/Tk, etc. compiler / assembler/ linker working. Memory mapping fundamentals. Power model Construction : ---------------------------------------------------------------------------------- There are two phases to SEA, one is the construction of the power model, the other is the use of the model. This section describes the construction phase. 1. Getting the core ready : (a) The core can be downloaded from SUN microsystems website. (The link has been removed for quite some time now. So I do not know whether distribution of the core is still allowed. ) (b) Preliminary compilation : The core from SUN comes with a ready-to-use toolkit, which obviously was for an antique OS and hence did not work. So a preliminary compilation/ debugging through ModelSim would help the user understand the various components of the core. The most important files are: system/rtl/sys.v : the toplevel file for the testbench. It contains the module description for the dram. The original file would give the details of how to implement your own model. Further description about the PLI models is given later. (search for DRAM-PLI) system/rtl/flash_prom32.v : this is flash module for the sparc. This is the first module that is used after the core boots up. (search for CLOCK-BOOT) A proper boot sequence has to be executed from this module if the microsparc has to start up. Sources : Boot-rom image file system/rtl/my_dram.v : this is the memory module All test programs / benchmarks have to be loaded to the sparc through this file. Uses the DRAM-PLI (search for DRAM-PLI) In the case of preliminary compilation, do not modify any source files, just check if the core gets compiled and if you need to adjust paths, ModelSim environment variables, etc. Detach all source files from their links to the toolkit provided by Sun. (Thats what I did. This involves removing / commenting out all instances of PLI-calls to the toolkit in all the source files ) After this is done the core will get compiled without any problems. (c) Compilation for simulation : There are several tasks that have to be performed before the core will start working. These are as follows : (1) Clock start up : Before the instruction squence is fetched from flash memory, the sparc spends several cycles in initializing the clock modules. The script to do this is here (search for CLOCK-BOOT) (2) Make sure that the sparc has been given proper clocks (verify this by checking the clock signals being recieved by various modules in the core, in the waveform window. There should be no floating clocks) (3) Once the clocks are setup, the boot-rom provides the first few instructions. These have to set-up the state of the micro-sparc. To set the sparc to a known state, you will have to program in ASM / binary and modify the boot_rom.imag file accordingly. Sources : Boot-rom image file Usually, you set the various control registers in various modules and then jump to a known address in the DRAM. Further instrcution fetch will now start from the DRAM. The address has to be set through modifications to linker that you are using (mapfiles) (search for COMPILATION) (4) Once you obtain the memory images for DRAM / flash memory, you can then start your simulation. Verify that the processor is indeed working as it should be (certain signals in the core, like instruction buses, address buses, alu IO buses, should indicate this.) 2. Building the Power model : (a) You can create different test cases in ASM / C (search COMPILATION) (b) Create the memory images for these test cases (search COMPILATION) (c) Start the simulation and verify that the testbench is working properly. (d) Hook up a power estimator (Sente) to ModelSim to gather gate-level transition data so that power estiamtion can be carried out by the tool. (search SENTE-HOOKUP) (e) Observe / collect data and build your model. (f) instruction and other trace data can be obtained through the use of PLIs. The reader must have become familiar with PLIs by now, so I am not giving any further details. Power model Usage : ---------------------------------------------------------------------------------- This section describes how to use the SEA framework for obtaining power profiles. Since I had used ModelSim as an instruction-set simulator as well, all the details below refer to that. The user can hook up his own instruction set simulator to get an instruction trace and use the power model. -- Please refer to scripts in the demo_tool_package. ---------------------------------------------------------------------------------- Specifics: DRAM-PLI : I used the PLI interface provided by ModelSim to create my own DRAM model. One has to be careful to verify the functionality of such a model through gate-level simulation of the core after one hooks up such a PLI. Sources : DRAM module, pli files CLOCK-BOOT: The microsparc takes one master clock signal and uses it to provide phase-shifted clocks to the entire core. This clock generation has been captured in the files : ssparc/clk_misc/ Considerable effort and help by David Penry (Princeton) culminated in the startup script. Sources : modelsim startup script for microsparc. COMPILATION: Since the toolkit that SUN provided could not be used (by me) I resorted to a using those provided for Leon, a sparc-compliant processor architecture from gaisler.com. Compilation / assembly of a tesbench should be no problem (refer to tool-user-guide). Linking is a phase that has to be tweaked for the microsparc. I have provided links to the scripts that I have used in my work. However use them with caution as a lot depends on how you have initialized your environment. I have provided the scripts for both working with ASM and C programs. The scripts for ASM (and hand-coding) were used to generate the boot-rom image files. The DRAM images were usually generated by those developed for C programs. Note that these scripts are not perfect in that they do not deal with the complete C language, nor all kinds of ASM files. The reason they were developed was to obtain power statistics for individual instructions under different scenarios such as loading from cache, memory, etc. The simple scripts developed for use with C programs, again are for simple C programs. These test the power model that we developed (based on simple test cases) in real-life situations. Anyway, the real-life C testbenches will / cannot be used for gate- level simulation because of their run-times. Sources : compile scripts SENTE-HOOKUP : In order to hook up the power estimator, the sparc core has to be first compiled with the verilog/vhdl compilers in Sente. Note that these are different from those used in ModelSim and have their own restrictions. The following readme describes the procedure to get Sente working Sources : sente startup scripts