/* ----------------------------------------------------- */

These scripts / files have been developed by Praveen Kalla,
University of Notre Dame, while working at NEC Laboratories
Inc. They are all covered by copyright laws pertaining to 
both institutions. They can be used for acadameic purposes
for free of cost, but not for commercial purposes.

The author does not assume any kind of responsibility for 
any damage through the use of these scripts / programs.

Some files might have been modified from their original form
as available at SUN Microsystems website. These files would
be covered under the copyright laws of SUN Microsystems as well

author contact 	: nkalla@cse.nd.edu (www.nd.edu/~nkalla)
advisors 	: Dr. Sharon Hu (www.nd.edu/~shu)
		: Dr. Joerg Henkel (henkel@nec-labs.com)

Do not remove this information from these files.

/* ----------------------------------------------------- */




/* ----------------------------------------------------- */

These scripts / files have been developed by Praveen Kalla,
University of Notre Dame, while working at NEC Laboratories
Inc. They are all covered by copyright laws pertaining to 
both institutions. They can be used for acadameic purposes
for free of cost, but not for commercial purposes.

The author does not assume any kind of responsibility for 
any damage through the use of these scripts / programs.

Some files might have been modified from their original form
as available at SUN Microsystems website. These files would
be covered under the copyright laws of SUN Microsystems as well

author contact 	: nkalla@cse.nd.edu (www.nd.edu/~nkalla)
advisors 	: Dr. Sharon Hu (www.nd.edu/~shu)
		: Dr. Joerg Henkel (henkel@nec-labs.com)

Do not remove this information from these files.

/* ----------------------------------------------------- */


/******************************************************************************/ 
/***  Description:
	the main memory model

Feb 11th rev : 64 bit op : 22 bit mem addr + 1 RAS

Initial File provided by SUN Microsystems. License agreements still hold.
Internal structure modified by Praveen Kalla.

****************************************************************************
****************************************************************************/


module	dram64(		
			ras_l,
			cas_l,
			addr,
			data,
			oe_l,
			we_l,
			) ;

	input [7:0] ras_l;
	input [3:0] cas_l;
	input [10:0] addr;
	input oe_l;
	input we_l;

	inout [63:0] data;
		
		//the memory config is that as indicated on pg 123 Usr manual
			//address regs
	reg [27:0] fulladdr;
	reg [2:0] ras_addr;
	reg [10:0] row_addr;
	reg [10:0] col_addr;
			
			//data regs
	reg [63:0] data_out;

	parameter ACCESS_TIME = 0;

			//recording the row_addr - and demuxing the ras
	event register_row_addr;
	event register_col_addr;
	event register_full_addr;
	event mem_event;

	always@(negedge ras_l[0])
		-> register_row_addr;
	always@(negedge ras_l[1])
		-> register_row_addr;
	always@(negedge ras_l[2])
		-> register_row_addr;
	always@(negedge ras_l[3])
		-> register_row_addr;
	always@(negedge ras_l[4])
		-> register_row_addr;
	always@(negedge ras_l[5])
		-> register_row_addr;
	always@(negedge ras_l[6])
		-> register_row_addr;
	always@(negedge ras_l[7])
		-> register_row_addr;
		
	always@(register_row_addr) 
		begin
			case(ras_l)
				8'b11111110 : ras_addr = 3'b000;
				8'b11111101 : ras_addr = 3'b001;
				8'b11111011 : ras_addr = 3'b010;
				8'b11110111 : ras_addr = 3'b011;
				8'b11101111 : ras_addr = 3'b100;
				8'b11011111 : ras_addr = 3'b101;
				8'b10111111 : ras_addr = 3'b110;
				8'b01111111 : ras_addr = 3'b111;
			endcase
			row_addr = addr;
		end
		
			//recording the col_addr
	always@(negedge cas_l[0])
		-> register_col_addr;
	always@(negedge cas_l[1])
		-> register_col_addr;
	always@(negedge cas_l[2])
		-> register_col_addr;
	always@(negedge cas_l[3])
		-> register_col_addr;


	always@( register_col_addr)
	begin
		col_addr = addr;
		-> register_full_addr;
	end

			//the assignment to the full_addr.
	always@( register_full_addr)
	begin 
		fulladdr = {ras_addr[2:0] , row_addr[10] , col_addr[10] , row_addr[9] , col_addr[9] , row_addr[8:0] , col_addr[8:0] , 1'b0 , 1'b0 , 1'b0} ;
		data_out = data;
		-> mem_event;
	end

	always@( mem_event)
	begin 
		begin
			$display("\n time: ",$time);
			$mem_access(fulladdr, data_out, oe_l, we_l, cas_l[1], cas_l[0]);

			if(oe_l == 1'b0) 
				$display(" Mem read (%h) @ (%h)", data_out , fulladdr);
			if(we_l == 1'b0)
				$display(" Mem write (%h) @ (%h)", data, fulladdr);
		end
	end

	assign #ACCESS_TIME data = (oe_l === 1'b0) ? data_out : 64'bz;

endmodule