Intellectual Property (IP)-based design methodologies combined with the
paradigm of platforms for specific application areas have enabled designers
to design new multi-million gate designs in shorter times and at an overall
smaller man-month count compared to traditional design methods that do
not extensively re-use existing IP. Examples of design platforms stem from
domains like multimedia processing, wireless communications, real-time
control, etc. The task of a designer has changed to integrating and estimating
various scenarios of a future complex System-on-Chip (SOC) by means of
re-using existing IP and design platforms. The designer can concentrate
more on high-level design space explorations rather than on re-coding already
available system IP components. This paradigm shift has triggered research
towards providing fast, high-level estimation and optimization strategies
for system parameters like area, time, energy and power as explained below.
Figure 1: System design flow
Any system design methodology would involve an important design cycle
as shown in Fig. 1. A system specification is initially transformed into
a set of tasks that could be implemented by different units. Cost metrics
such as area and power; and performance metrics such as timing are estimated.
Repartitioning is done if necessary and the design is re-evaluated. The
efficiency of this cycle usually depends on effective feedback from the
estimation-and-analysis sub-task. In particular we address this problem
in regards to system-on-chip design where tools working at different tasks
such as partitioning, scheduling, code transformations, etc. targeting
energy behavior of the system, would benefit tremendously from a per-cycle
energy behavior of the embedded processor-core which is one of the most
important components of such a system. Many embedded systems typically
have such a configuration where a processor core is tightly integrated
with application-specific engines.
In this project we analyze a publicly available soft core, MicroSparcIIep,
in regards to its power behaviour. Based on the implementation features
of the core, we have developed a power estimation framework, SEA,
which can be used to provide accurate energy estimates for an application
with an accuracy of 95%. It can also provide per-cycle power behaviour
but with a greater error of around 15%. Compared to commercial power estimators
like WattWatcher from SequenceDesign,
SEA can provide fast estimates once a power database has been built and
incorporated into the framework.
MicroSparcIIep
We have used a publicly available, synthesizable model of the MicroSparcIIep
core as an example. Employing a commercial core allows us to study many
architectural features that typically do not appear in simple processor
models constructed for research purposes only. It is a RISC architecture
and integrates the SPARC processor with a floating-point unit (FPU), memory
management unit (MMU), separate instruction and data caches, PCI bus controller
(PCIC), DRAM and flash memory controller, and a clock generator, onto a
single device.
SEA
The framework provides for
Building a power database for a given soft core.
A per-cycle instruction-level power estimation model.
Energy/power estimation for applications in C.
The SEA Tool Flow:
1. A high level code such as C or ASM is compiled
and prepared for the microSparcIIep
soft core.
2. Prediction Flow: (left side of Fig. 2) : This flow is used
for normal use for obtaining power estimates.
An instruction set simulator is used to obtain the instruction
trace for the application.
Power databases which have been constructed after extensive
experimentation are used along with the instruction trace to obtain
power behavior.
3. Estimation Flow: (right side of Fig. 2) : This flow is used for
database construction or for verification purposes.
A RTL simulator is used
to obtain switching activity from the soft core.
The activity trace is used along with power libraries by a commercial
power estimator to obtain per-cycle power behaviour of the core.
The results are used to construct the power database which is used in the
``Prediction Flow''.
Figure 2: SEA Tool Flow
SEA is built around several commercial tools
Leon
compiler tool suite : This tool suite is used to compile the
C applications / ASM code for the SPARC architecture.
MicroSparcIIep mapper: In-house tools
have been developed to re-map the code for microSparcIIep. Any new soft
core would need to modify these mappers in order to utilize the SEA framework.
Vsim
from Model Technology : This HDL simulator is used for providing accurate
gate-level activity information regarding the soft core. Along with the
use of PLI interfaces, instruction traces can also be generated for the
soft core during simulation. A traditional instruction-set-simulator can
also be used for the later purpose.
Watt-watcher
from Sequence Design : Commercial power estimators such as these can
be used in order to obtain accurate power behaviour of the core in order
to construct the power databases.
SEA Demo
A sample project can be tried here. Since SEA
depends on certain tools which cannot run without licenses, pre-computed
data files are used to generate the plots. The idea is to give the reader
an insight into the workings of SEA.
References
P. Kalla, J. Henkel and X. Sharon Hu, ``SEA: Fast Power Estimation for
micro-architectures (Extended Abstract)'', 5th Intl. Conf. on ASIC
(ASICON), (Invited Talk) Oct. 2003.
P. Kalla and J. Henkel and X. Hu, ``SEA: Fast Power Estimation for Micro-Architectures'',
Asia South Pacific Design Automation conference (ASPDAC
) Jan. 2003.
P. Kalla, ``Power analysis of soft cores'', Dept. of Computer Sci.
and Engg., University of Notre Dame, MS Thesis, Nov. 2002.
P. Kalla, J. Henkel and X. Hu, ``Micro-Architectural
Power Estimation for C-based Design Flow'', REPORT no. 2002-C037-4-5110-2,
NEC CCRL, Aug. 2002.
