|
Sunday, June 11, 2006
|
8:30
|
|
Welcome
and Opening Remarks
Wolfgang Porod (Notre Dame), Chair of SNW
2006
Asen Asenov (Univ. of Glasgow) Program Chair
|
Session 1: Nano CMOS
Devices (Session Chair: T. Skotnicki)
|
8:40
|
1-1
|
(Invited)
Silicon Nanoelectronics: Past, Today and Future, Y. Nishi
(Stanford University) |
9:10
|
1-2 |
10-nm-Gate-Length n-Type
Schottky Barrier MOSFETs with High Current Drivability, M. Jang,
Y. Kim, M. Jun, C. Choi, T. Kim, B. Park and S. Lee (ETRI)
|
9:30
|
1-3 |
CMOS Integration of
L=32nm Strained-Si MOSFET on Si0.8Ge0.2 SRB for Low Voltage Applications,
F. Payet, F.Boeuf, N.Villani, N. Loubet, J.M. Hartmann, J. Rosa, R. Ranica,
A. Pakfar, K. Romanjek, A. Cros, S. Pokrant, F. Leverd, F. Salvetti, T.
Skotnicki (STMicroelectronics, CEA/LETI)
|
9:50
|
1-4 |
Undoped Channel PMOS
FinFET with Deposited Titanium Nitride Gate Electrode over SiO2 Gate Dielectric
for Low Leakage Applications, L. Mathew, S. Kalpat, T. Stephens,
R. Noble, M. Jahanbhani, B. Goolsby, R. Mora, M. Sadd, R. Rai, S. Becker,
C. Parker, V.P. Trivedi, D. Sing, B-Y. Nguyen, R. Shimer, Z. Shi, J. Vasek,
L. Prabhu, R. Garcia, M.M. Chowdhury, J.G. Fossum (ASTS Freescale Semiconductor
Inc., Univ. of Florida)
|
10:10 |
|
Coffee Break
|
Session
2: Nanodevice Transport and Physics (Session Chair: K.
Ushida)
|
10:30
|
2-1 |
Injection Velocity Optimization
in Quasi-Ballistic Si-nMOSFETs, M. Ferrier, R. Clerc, Q. Rafhay,
F. Daugé, G. Pananakakis, G. Ghibaudo, F. Boeuf, T. Skotnicki
(IMEP, STMicroelectronics)
|
10:50
|
2-2 |
Experimental Study on
Breakdown of Mobility Universality in <100>-Directed (110)-Oriented
pMOSFETs, K. Shimizu, G. Tsutsui, D. Januar, T, Saraya and T. Hiramoto
(Univ. of Tokyo)
|
11:10
|
2-3 |
MC Simulations of High
Performance In0.3Ga0.7As Nano-MOSFETs for Low-Power CMOS Applications,
K. Kalna, J.A. Wilson, D.A.J. Moran, R. Hill, A.R. Long, R. Droopad, M.
Passlack, I.G. Thayne, and A. Asenov (Univ. of Glasgow, Freescale Semiconductor
Inc.)
|
11:30
|
2-4 |
Impact of Parameter
Variations and Random Dopant Fluctuations on Short-Channel Fully-Depleted
SOI MOSFETs with Extremely Thin BOX, T Ohtou, N. Sugii, and T.
Hiramoto (Univ. of Tokyo, Hitachi, Ltd.)
|
11:50
|
2-5 |
Comparative Study of
Low-Field Mobilities in Double- and Single-Gate Ultra-Thin Body SOI for
Different Substrate Orientations, V. Sverdlov, E. Ungersboeck,
H. Kosina, and S. Selberherr (TU Wien)
|
12:10
|
2-6 |
|
12:30 |
|
Lunch Break
|
Session
3: Quantum and Coulomb Blockade Devices (Session Chair:
T. Hiramoto)
|
1:50
|
3-1 |
(Invited)
Demonstration of the First Quantum Dot Based Charge Qubit in Si,
David Williams (Hitachi Cambridge) |
2:20
|
3-2 |
Room-Temperature Operation
of Data Processing Circuit Based on Single-Electron Transfer and Detection
with Metal-Oxide-Semiconductor Field-Effect-Transistor Technology,
K. Nishiguchi, A. Fujiwara, Y. Ono, H. Inokawa, and Y. Takahashi (NTT
Corporation, Hokkaido Univ.) |
2:40
|
3-3 |
Coulomb Blockade Oscillations
in Gate-All-Around Silicon Nanowire MOSFETs, V. Pott, J. Boucart,
D. Bouvet, K.E. Moselund and A.M. Ionescu (Ecole Polytechnique Fédérale
de Lausanne) |
3:00 |
|
Coffee Break
|
Session
4: Nano Photonics (Session
Chair: E. Suzuki)
|
3:20
|
4-1 |
(Invited)
Phonons in Si Nanowires and SiGe Quantum Dot Superlattices,
Alexander Balandin (Univ. of California at Riverside)
|
3:50
|
4-2 |
Effect of Photo-Induced
Charges on Single-Hole-Tunneling Current of an SOI-FET, Z.A. Burhanudin,
R. Nuryadi, and M. Tabe (Shizuoka Univ.)
|
4:10
|
4-3 |
Co-Integration of Gate-All-Around
MOSFETs and Local Silicon-On-Insulator Optical Waveguides on Bulk Silicon
for GHz On-Chip Optical Signaling, K.E. Moselund, L. Tschuor, D.
Bouvet, V. Pott, P. Dainesi, C. Eggimann, N. Le Thomas, R. Houdré,
and A.M. Ionescu (Ecole Polytechnique Fédérale de Lausanne)
|
4:30-6:00 |
Session 5: Poster
Session, Starting with Short Oral Presentations (Session
Chair: D. Ferry)
|
| |
5-1 |
Effects of the Low-Field
Mobility in Single-Gate and Double-Gate Ultrathin-Body MOSFETs Scaled to
the Ultimate Technology Nodes, S. Reggiani, E. Gnani, M. Rudan
and G. Baccarani (Univ. of Bologna)
|
| |
5-2 |
Design and Analysis
of Functional NEMS-gate MOSFETs and SETs, B. Pruvost, H. Mizuta,
and S. Oda (Tokyo Institute of Technology, SORST JST)
|
| |
5-3 |
Impact of Structure
Relaxation on Performance of Silicon Nanowire FETs, G. Liang, D.
Kienle, S. Patil, J. Wang, A.W. Ghosh, and S. Khare (Purdue Univ., Univ.
of Toledo, Univ. of Virginia)
|
| |
5-4 |
ILD Mechanical Stress
Effect on the Reliability of Nano-scale CMOSFETs, I.-S. Han, H.-H.
Ji, T.-G. Goo, H.-S. Joo, Y.-G. Kim, S.-H. Park, H.-S. Lee, J.-S. Wang,
and H.-D. Lee (Chungnam National Univ., Magnachip Semiconductor Ltd.)
|
| |
5-5 |
Four-Terminal FinFETs
Fabricated Using an Etch-Back Gate Separation, K. Endo, Y. Ishikawa,
Y. Liu, K. Ishii, T. Matsukawa, S. Ouch, M. Masahara, E. Sugimata, J. Tsukada,
H. Yamauchi, and E. Suzuki (AIST)
|
| |
5-6 |
SET/FET-Based Flexible
Multi-Valued NAND Logic Gates, C.K. Lee, S.J. Kim, J.U. Lee, S.J.
Choi, J.H. Hwang, S.E. Lee, S.D. Lee, J.B. Choi, Y.S. Yu, H.W. Kye, B.N.
Song (Chungbuk National Univ., Hankyong National Univ., EXCEL Semiconductor
Inc.)
|
| |
5-7 |
Resonant Tunneling Diodes
Formed by Fluoride Heterostructures for Co-Integration with CMOS Devices,
K. Tsutsui, S. Watanabe, T. Sugisaki, Y. Toriumi and M. Maeda (Tokyo
Institute of Technology, Kochi Univ. of Technology)
|
| |
5-8 |
Effects of Oversized
Bottom Gate in Self-Aligned Gate-All-Around MOSFET, J.Y. Song,
W.Y. Choi, J.H. Park, J.P. Kim, J.D. Lee, and B.-G. Park (Seoul National
Univ.)
|
| |
5-9 |
Withdrawn
|
| |
5-10 |
A Study of Quantum Transport
in End-of-Roadmap DG-MOSFETs Using a Fully Self-Consistent Wigner Monte
Carlo Approach, D. Querlioz, J. Saint-Martin, V. Nam Do, A. Bournel
and P. Dollfus (Univ. Paris Sud)
|
| |
5-11 |
Thermal Stability Improvement
of Nickel Germanosilicide Utilizing Ni-Pd Alloy for Nano-Scale CMOS Technology,
Y.-J. Kim, S.-Y. Oh, W.-J. Lee, Y.-Y. Zhang, Z. Zhong, S.-Y. Jung, H.-H.
Ji, H.-S. Cha, Y.-C. Kim, J.-S. Wang, and H.-D. Lee (Chungnam National
Univ., Magnachip Semiconductor Ltd., Korea Univ. of Technology and Education)
|
| |
5-12 |
Fabrication and Characterization
of Tri-Gate Field-Induced Inter-band Tunneling Effect Transistors (TG-FITETs),
S.-H. Song, K.R. Kim, J.H. Kim, S. Kang, K.C. Kang, J.D. Lee, H. Shin, and
B.-G. Park (Seoul National Univ., Stanford)
|
| |
5-13 |
Selective Solid-Phase
Epitaxy of Ultra-Shallow p+ Aluminum-Doped Silicon Junctions for Integration
in Nanodevices, Y. Civale, L.K. Nanver, P. Hadley (DIMES, Delft
Univ. of Technology)
|
| |
5-14 |
Single-Charge Pump Operation
by Random-Multidot-Channel FET, H. Ikeda, K. Yokoi and M. Tabe
(Shizuoka Univ.)
|
| |
5-15 |
Modified Saddle MOSFET
for High-Performance and High-Density Sub-50 nm DRAM Cell Transistors,
K.-H. Park, K.-R. Han, Y.M. Kim, and J.-H. Lee (Kyungpook National Univ.)
|
| |
5-16 |
Nano-Charge-Trapping
Devices Fabricated by One-Step Oxidation on Poly-SixGe1-x, C.S.
Lai, C. S. Huang, K.M. Fan, T.M. Pan, C.H. Kao, Z.-G. Lin, C.-S. Chang and
C.-P. Chou (Chang Gung Univ., National Chiao Tung Univ.)
|
| |
5-17 |
Atomistic Approach to
Thickness-Dependent Bandstructure Calculation of InSb UTB, X. Guan
and Z. Yu (Tsinghua Univ.)
|
| |
5-18 |
Low Temperature Fabrication
of Si Nanocrystal Dots For Floating Gate Memory, K. Ichikawa, M.
Mukai, P. Punchaipetch, H. Yano, T. Hatayama, Y. Uraoka, T. Fuyuki, A. Tomyo,
E. Takahashi, T. Hayashi, and H. Harima (Nara Institute of Science and
Technology, Nissin Electric Co., Ltd., Kyoto Institute of Technology)
|
| |
5-19 |
Threshold Voltage Modeling
of Bulk FinFETs by Considering Corner Effect, B.-K. Choi, Y.M.
Kim, K.-R. Han, Y.J. Park and J.-H. Lee (Kyungpook National Univ., Seoul
National Univ.)
|
| |
5-20 |
Analysis of Two Alternative
Scaling Strategies for Sub-30 nm Double-Gate SOI MOSFETs, N. Barin,
M. Braccioli, C. Fiegna, E. Sangiorgi (Univ. of Ferrara, Univ. of Bologna)
|
| |
5-21 |
Two-Dimensional Carrier/Dopant
Profiling by Kelvin-Probe Force Microscopy, C.-M. Hsieh, B.-Y.
Tsui, P.-C. Su, S.-D. Tzeng, and S. Gwo (National Chiao Tung Univ.,
National Tsing-Hua Univ.)
|
| |
5-22 |
Kinetic Monte Carlo
(KMC) for Understanding Boron Up-Hill Diffusion After Germanium Pre-Amorphization,
J.-S. Kim and T. Won (Inha Univ., National IT Research Center for Computational
Electronics)
|
| |
5-23 |
Off-State Leakage Mechanism
in Novel Si Nanowire Transistors with Solid-Phase Crystallized Channels,
H.-C. Lin, M.-H. Lee, C.-J .Su, J.-H, Tsai, J.-J. Hung, Raymond C.-T. Lin,
S.-W. Shen, and T.-Y. Huang (National Chiao Tung Univ., National Nano
Device Laboratories)
|
| |
5-24 |
1/f Noise Characteristics
of Sub-100 nm MOS Transistors, J.-H. Lee, S.-Y. Kim, I. Cho, S.
Hwang, and J.-H. Lee (Kyungpook National Univ., Magnachip Semiconductor
Ltd.)
|
| |
5-25 |
Nano-Scale Resistive
Probe for Recording Applications, J. Kim, Y. Jung, S. Hong, J.
Jung, B.-G. Park, J. D. Lee, and H. Shin (Seoul National Univ., Samsung
Advanced Institute of Technology)
|
| |
5-26 |
Effects of Non-Parabolicity
on the Energy Levels in a Quantum Dot, F.M. Gómez-Campos,
S. Rodríguez-Bolívar, J.E. Carceller (Universidad de Granada)
|
| |
5-27 |
Interconnect-Driven
Nanoelectronic Circuits, W. Wang (Indiana Univ., Purdue Univ.)
|
| |
5-28 |
Antenna-Coupled Metal-Oxide-Metal
Diodes for Terahertz Detection, J.A. Bean, B. Rakos, G.H. Bernstein,
P. Fay, W. Porod (Univ. of Notre Dame)
|
| |
5-29 |
Double-Logarithm 1/E
Model: A New Empirical Unified Oxide Reliability Model, L.-M. Wang
(Jiangsu College of Information Technology)
|
| |
5-30 |
First-Principle Calculation
on Migration Energy for Indium Diffusion in Silicon, K.-S. Yoon,
C.-O. Hwang and T. Won (Inha Univ., Soongsil Univ.)
|
| |
5-31 |
Experimental Demonstration
of a Single-Electron Latch with Granulated Film Cotunneling Suppressor,
A.O. Orlov, X. Luo, K.K. Yadavalli, and G.L. Snider (Univ. of Notre
Dame)
|
| |
5-32 |
Transport in Silicon
Nanowires: Surface Roughness and Confined Phonons, E.B.
Ramayya, D.Vasileska, S.M. Goodnick, and I. Knezevic, (Univ. of Wisconsin-Madison,
Arizona State Univ.) |
| |
5-33 |
Experimental Study of
Two-Dimensional Confinement Effects on Reverse-Biased Current Characteristics
of Ultra-Thin Film Lubistors, Y. Omura, (Kansai Univ.)
|
Monday,
June 12, 2006
|
Session
6: Nanoscale Memories (Session
Chair: H. Mizuta)
|
8:30
|
6-1 |
Floating Gate Memory
Device Based on Biomineralized Nanodots Embedded in High-k Gate Oxides,
P. Punchaipetch, T. Hikono, Y. Uraoka, T. Fuyuki, S. Yoshii and I. Yamashita
(Nara Institute of Science and Technology, Matsushita Electric Co. Ltd.)
|
8:50
|
6-2 |
Improved Window with
a P-doped Control Gate in a Nano-Crystal Split-Gate Memory, M.
Sadd, J.A. Yater, R.F. Steimle, E.J. Prinz, T. Kirichenko, C.T. Swift, R.
Rao, R. Muralidhar, K. Chang (Freescale Semiconductor Inc.)
|
9:10
|
6-3 |
Long-Retention Gain-Cell
DRAM Using Undoped SOI MOSFET, K. Nishiguchi, A. Fujiwara, Y. Ono,
H. Inokawa, and Y. Takahashi (NTT Corporation, Hokkaido Univ.)
|
9:30
|
6-4 |
New Capacitor-less 1T
DRAM Cell : Surrounding Gate MOSFET with a Vertical Channel (SGVC Cell),
H. Jeong, K.-W. Song, I.H. Park, T.H. Kim, Y.S. Lee, S.-G. Kim, J. Seo,
K. Cho, K. Lee, H. Shin, J.D. Lee, and B.-G. Park (Seoul National Univ.,
Samsung Electronics Co., LTD.)
|
9:50
|
6-5 |
Fabrication and Characterization
of Nanoscale Suspended Floating Gates for NEMS Memory, N. Momo,
T. Nagami, S. Matsuda, Y. Tsuchiya, S. Saito, T. Arai, Y. Kimura, T. Shimada,
H. Mizuta, and S. Oda, (Tokyo Institute of Technology, Hitachi Ltd.,
SORST-JST)
|
10:10
|
6-6 |
√RAM: A Quasi
Non Volatile Low Power Memory Cell, G. Bossu, C. Charbuillet, R.
Ranica, A. Villaret, D. Chanemougame, S. Monfray, S. Borel, F. Leverd, P.
Masson, P. Mazoyer and T. Skotnicki (STMicroelectronics, CEA LETI, IMT
Technopôle)
|
10:30
|
6-7 |
Electro-Mechanical Simulation
of Programming/Readout Characteristics for NEMS Memory, T. Nagami,
N. Momo, Y. Tsuchiya, S. Saito, T. Arai, T. Shimada, H. Mizuta, and S. Oda
(Tokyo Institute of Technology, SORST-JST, Hitachi Ltd, Quantum 14 Co. Ltd.)
|
10:50 |
|
Coffee Break
|
Session
7: Nano Device Fabrication (Session Chair: K. De Meyer)
|
11:10
|
7-1 |
(Invited),
Impurity Conduction and its Control in SOI Mosfets; Towards Silicon
Single-Dopant Electronics, Yukinori Ono (NTT BRL)
|
11:40
|
7-2 |
Study of La2O3 Gate
Dielectric Suitability for Future MIM and MOSFETs, K. Kakushima,
P. Ahmet, J.–A. Ng, J. Molina, H. Sauddin, Y. Kuroki, K. Nakagawa,
A. Fukuyama, K. Tachi, Y. Shiino, J. Song, K. Tsutsui, N. Sugii, T. Hattori
and H. Iwai (Tokyo Institute of Technology)
|
12:10
|
7-3 |
Mechanism of Fermi-Level
Pinning for n-like Metal Silicides on Hf-Based Gate Dielectrics,
K. Shiraishi, H. Takeuchi, Y. Akasaka, H. Watanabe, N. Umezawa, T. Chikyow,
Y. Nara, T.-J. King Liu, and K. Yamada (Univ. of Tsukuba, NIMS, Univ.
of California, Selete, Osaka Univ., Waseda Univ.)
|
12:30
|
|
Lunch Break
|
Session
8: Post Roadmap Devices (Session Chair: M. Tabe)
|
1:50
|
8-1 |
(Invited)
Silicon Strips and Curls for Novel Circuitry, Robert Blick
(Wisconsin)
|
2:20
|
8-2 |
Schottky-Contact Silicon
Nanowire Field Effect Transistor Test Structures, S.-M. Koo, C.A.
Richter, Q. Li, M.D. Edelstein, E.M. Vogel (National Institute. of Standards
and Technology, Kwangwoon Univ.)
|
2:40
|
8-3 |
Effects of High-k (HfO2)
Gate Dielectric in Double-Gate and Cylindrical-Nanowire MOSFETs Scaled to
the Ultimate Technology Nodes, E. Gnani, S. Reggiani, M. Rudan
and G. Baccarani (Univ. of Bologna)
|
3:00
|
8-4 |
Fabrication and Evaluation
of Si Nanobridge Transistor, J. Ogi, N. Momo, M.A.H. Khalafalla,
Y. Tuchiya, H. Mizuta, S. Oda (Tokyo Institute of Technology, and SORST-JST) |
3:20
|
|
Coffee Break
|
Session
9: Nano Device Characterization (Session Chair: T. J.
King)
|
3:40
|
9-1 |
In-Depth Characterization
of 3D Stacked MOSFETs by Coulomb Blockade Spectroscopy, M. Hofheinz,
X. Jehl, M. Sanquer, R. Cerruti, A. Cros, P. Coronel, H. Brut, and T. Skotnicki
(CEA-Grenoble, STMicroelectronics)
|
4:00
|
9-2 |
Novel Analysis Technique
of Dopant Distribution in Nano-Scale FinFET and Evaluation Dopant Diffusion
and Dose Loss During Thermal Annealing, T. Izumida, K. Okano, T.
Kanemura, M. Kondo, S. Itoh, N. Aoki, H. Kawasaki, A. Kaneko, A. Yagishita,
S. Inaba, K. Ishimaru, M. Nakamura, K. Eguchi, K. Suguro, and H. Ishiuchi
(Toshiba Corporation Semiconductor Co.)
|
4:20
|
9-3 |
Electrical Characterization
of Ordered SI:P Dopant Arrays, W. Pok, T.C.G. Reusch, G. Scappucci,
F. J. Rueß, A.R. Hamilton, and M.Y. Simmons, (Univ. of New South
Wales)
|
4:20-6:00
|
Session 10:
Poster Session, Starting with Short Oral Presentations (Session
Chair: D. J. Frank)
|
| |
10-1 |
Precise Manipulation
and Alignment of Single Nanowires for Device Fabrication, Q. Li,
S.-M. Koo, C.A. Richter, M.D. Edelstein, J.J. Kopanski, J.S. Suehle and
E.M. Vogel (NIST, Kwangwoon Univ.)
|
| |
10-2 |
The Impact of Random
Dopant Aggregation in Source and Drain on the Performance of Ballistic DG
Nano-MOSFETs: A NEGF Study, A. Martinez, J.R. Barker, A. Svizhenko,
M. P. Anantram and A. Asenov (Univ. of Glasgow, Stanford Univ., Nasa
Ames Research Center)
|
| |
10-3 |
2-Bit/Cell Characteristics
of Highly Scalable SONOS Memory Devices with Spacer-type Nitride Layer in
Recess Channel Region, K.-R. Han, Y.-M. Kim, S.-G. Jung, K.-H.
Park, S.-W. Kong, I. Cho, and J.-H. Lee (Kyungpook National Univ., SILVACO
International Co., Ltd., Seoul National Univ.)
|
| |
10-4 |
Multi-Gate FET Design
for Tolerance to Statistical Dopant Fluctuations, V.Varadarajan,
L. Smith, S. Balasubramanian and T.-J. King Liu (Univ. of California,
Synopsys, Inc.)
|
| |
10-5 |
Design and Fabrication
of Asymmetric MOSFETs Using a Sidewall Spacer, J.P. Kim, W.Y. Choi,
J.Y. Song, J.H. Park, J.D. Lee, and B.-G. Park (Seoul National Univ.)
|
| |
10-6 |
A Quantitative Model
for Silicon Using Non-Orthogonal Extended Hückel Theory, D. Kienle,
J. Cerda, K. Bevan, G. Liang, L. Siddiqui, and A.W. Ghosh (Purdue Univ.,
Instituto de Ciencia de Materiales de Madrid, Univ. of Virginia)
|
| |
10-7 |
Towards MOS Memory Devices
Containing 1 nm Silicon Nanoparticles, O.M. Nayfeh, D.A. Antoniadis,
K. Mantey and M.H. Nayfeh (Massachusetts Institute of Technology, Univ.
of Illinois at Urbana-Champaign)
|
| |
10-8 |
Double-Gate SOI FinFETs
Using Sidewall Multi-Line Patterning Technique, J.H. Park, W.Y.
Choi, J.Y. Song, J.P. Kim, J.D. Lee, and B.-G. Park (Seoul National
Univ.)
|
| |
10-9 |
A New Recessed FinFET
with R-Shaped Side Channel (RFinFET) for DRAM Cell Applications,
M.J. Lee, S. Jin, C.-K. Baek, I.-Y. Chung, Y.J. Park, and H. S. Min (Seoul
National Univ., Gyeongsang National Univ.)
|
| |
10-10 |
Low Temperature Template
Synthesis of Germanium Nanowires for 3-D Integration, H. Jagannathan,
H.-C. Kim, E.M. Freer, L. Sundstrom, T. Topuria, P.M. Rice, M. Deal1, Y.
Nishi (Stanford Univ., Almaden Research Center.)
|
| |
10-11 |
On the Feasibility of
Nanoscale FinFETs for RF Applications, A. Kranti and G.A. Armstrong
(Queen's Univ. of Belfast)
|
| |
10-12 |
Electron Mobility Model
for <110> Stressed Si Including Strain-Dependent Mass, S.
Dhar, E. Ungersboeck, H. Kosina, T. Grasser, and S. Selberherr (Institute
for Microelectronics, TU Vienna)
|
| |
10-13 |
Single-Electron Tunneling
in a SOI-MOSFET Embedding Artificial Dislocation Network, R. Nuryadi,
C. Yamamoto, Y. Ishikawa, and M. Tabe (Shizuoka Univ., Univ. of Tokyo)
|
| |
10-14 |
Flash Memory Device
with ‘I’ Shape Floating Gate for Sub-70nm NAND Flash Memory,
S.-G. Jung, K.-R. Han, K.-H. Park and J.-H. Lee (Kyungpook National
Univ.)
|
| |
10-15 |
Critical Substrate Bias
in Variable Threshold-Voltage CMOS with Short Channel FD SOI MOSFETs,
A.T. Putra, T. Ohutou, T. Hiramoto (Univ. of Tokyo)
|
| |
10-16 |
Continuum Versus Quasi-Bound
State Tunneling in Novel Device Architectures, M. Karner, A. Gehring,
S. Holzer1, M. Wagner, and H. Kosina (TU Wien, AMD Saxony)
|
| |
10-17 |
Influence of Interface
and Oxide Traps on Negative Bias Temperature Instability, R. Entner,
T. Grasser, H. Enichlmair, and R. Minixhofer (TU Wien, Austriamicrosystems)
|
| |
10-18 |
Impact of the Scattering
on Nano-Scale Ultra-Thin-Body Schottky-Barrier MOSFETs, X.Y Liu,
Z.L. Xia, G. Du, J.F. Kang, R.Q. Han (Peking Univ.)
|
| |
10-19 |
Effects of Seeding Window
Arrangement on the Performance of Si Nanowire Transistors with MILC Channels,
C.-J. Su, H.-C. Lin, M.-H. Lee, H.-H. Tsai, R.C.-T. Lin, S.-W. Shen, C.-C.
Lee, T.-Y. Huang, and Y.-S. Yang (National Chiao Tung Univ.)
|
| |
10-20 |
Kinetic Lattice Monte
Carlo Simulations of Germanium Island Growth on Prepatterned Silicon (100)
Substrates, R. Akis and D.K. Ferry (Arizona State Univ.)
|
| |
10-21 |
Non-Abelian Operations
in Silicon Quantum Devices, A. Cummings, R. Akis, and D.K. Ferry
(Arizona State Univ.)
|
| |
10-22 |
Extraction of Substrate
Resistance in Bulk FinFETs Through RF Modeling, J.-H. Jung and
J.-H. Lee (Kyungpook National Univ.)
|
| |
10-23 |
Static Noise Margin
of SRAM Cells with 35 nm SOI FinFETs, Y. Li, and C.-S. Lu (National
Chiao Tung Univ.)10-24 Modeling Ballistic Transport in Nanoscale MOSFET
Devices, T.-W. Tang and P. Samra (Univ. of Massachusetts)
|
| |
10-25 |
A New Design Architecture
of Novel Nanoscale Device to Reduce Leakage Currents, D. Datta,
S. Ganguly, A.A.P. Sarab, D. Sarkar, and S. Dasgupta (Indian School
of Mines, Indian Institute of Roorkee)
|
| |
10-26 |
Electrical Characteristics
on Ellipse-Shaped-Surrounding-Gate Nanowire FinFETs, Y. Li, and
W.-H. Chen (National Chiao Tung Univ.)
|
| |
10-27 |
Characteristics of Silicon
Schottky-Barrier MOSFET Inverter by Selective Surface Modification,
J.T. Sheu, C.C. Chen, W.-H. Chen, and M.L. Sheu (National Chiao Tung
Univ., National Chi Nan Univ.)
|
| |
10-28 |
Quantum Simulation of
Device Characteristics of Si Nanowire FETs, M. Shin (Information
and Communications Univ.)
|
| |
10-29 |
An Improvement for Solving
the Non-Parabolic Schrödinger Equation in Quantum Wells, S.
Rodríguez-Bolívar, F.M. Gómez-Campos, J.E. Carceller
(Univ. of Granada)
|
| |
10-30 |
Demonstration of a Silicon-Based
Quantum Cellular Automata Cell, M. Mitic, M.C. Cassidy, K.D. Petersson,
E. Gauja, R.P. Starrett, R. Brenner, C. Yang, D.N. Jamieson, R.G. Clark
and A.S. Dzurak (Univ. of New South Wales, Univ. of Melbourne)
|
| |
10-31 |
Silicon Nanocrystals-Embedded
Mesoporous Silica for Ultraviolet Light Detection, Y.-F. Lai, J.-M.
Shieh, A.-T. Cho, and B.-T. Dai, (National Nano Device Laboratories)
|
