Invited Presentations, Unreferreed Workshops, Unreferreed or Abstract referred Conference Articles for Peter M. Kogge:

Keynotes and Invited Talks

  1. Kogge, Peter M., “Architectural Challenges at the Exascale Frontier,” Invited talk, STF'08 - Simulating the Future; Using One Million Cores and Beyond, 22-24 September 2008, Château de Tremblay, France.
  2. Kogge, Peter M., “From Petaflops to Exaflops,” Invited Keynote, Int. Supercomputing Conf. (ISC'08),  June 20, 2008, Dresden, Germany
  3. Kogge, Peter M., “Exascale -- The Next Great Challenge,” DOE Salishan HPC Conference, Oregon, April 14, 2008
  4. Kogge, Peter M., “The Shape of Things to Come: The Future of Microarchitectures for HPC Systems,” Invited talk, 13th SIAM Conf. on Parallel Processing for Scientific Computing, March 12, 2008 Atlanta, GA.
  5. Kogge, Peter M., “The Shape of Things to Come: Future Trends in HPC Architectures,” Keynote DOE/DOD Workshop on Emerging Architectures and Applications, Nov. 29-30, 2007, Washington, DC.
  6. Kogge, Peter M., "Past Predictions, the Present, and Future Trends in HPC Microarchitectures," Argonne National Labs, March 7, 2007.
  7. Kogge, Peter M., "Past Predictions, the Present, and Future Trends," Keynote, High Performance Computing Workshop on Programming Languages, Sandia National Labs, Albuquerque, New Mexico, Dec. 11-12, 2006.
  8. Kogge, Peter M., "Intellectual Property and The University-Related Startup," Lecture series on "The Law and ..", Law School, Univ. of Notre Dame, March 22, 2006.
  9. Kogge, Peter M., "An Introduction to Multi-core Designs," Advanced Circuits Forum on Multicore Architectures, Designs, and Implementation Challenges, Int. Solid State Circuits Conf. (ISSCC), San Francisco, Feb. 10, 2006.
  10. Kogge, Peter M., "Long Term Trends in Computer Architecture Research Funding as Seen thru ISCA," invited talk, CRA Workshop on Funding in Computer Architecture, Aptos, CA,: Dec. 4-7, 2005
  11. Kogge, Peter M., "PIMs and CMPs for Petaflops: How Many Cores Can/Should We Place on the Head of a Pin, and why?" invited talk, Salishan High Speed Computing Conference, Oyster Bay, OR, April 18-21, 2005.
  12. Kogge, Peter M., "The Nano Revolution and Its Effects on Micro/Nano Systems Education," Invited Talk, ASEE New England Regional Conf., Fairfield Univ., Conn, April 8,2005.
  13. Kogge, Peter M., "Advanced Architectures & Execution Models: How New Architectures May Help Give Silicon Some Temporary New Life and Pave the Way for New Technologies," Invited Talk, Workshop on Extreme Computing, Fifth LACSI Symposium, Santa Fe, New Mexico, October 12, 2004.
  14. Kogge, Peter M., Invited Keynote Speech, "The Nano Revolution and Its Effects on Micro/Nano Systems Education," IEEE Microsystems Education Conference (MSE), Anaheim, CA, June 1, 2003.
  15. Kogge, Peter M., Invited Keynote Speech, "The State of State," HPCA09, Anaheim, CA, Feb. 12, 2003.
  16. Kogge, Peter M., "The Future of Computing," Invited talk at Lawrence Livermore National Lab's, Physics and Advanced Technologies Directorate, PAT Luminaries Day in conjunction with LLNL's 50th anniversary, June 28, 2002. Also at Sandia National Labs, Oct. 29, 2002.
  17. Kogge, Peter M., "On Removing the Magic from FORTH," invited keynote speech, 3rd Annual FORTH Conference, San Jose, CA, Oct. 1982

Workshops with published proceedings

  1. Kogge, Peter M., "Some Initial Explorations into the Hierarchical Multi-Core Chip Design Space for HPC Systems," International Workshop on Innovative Architectures (IWIA'07), Maui, HI, Jan. 11-12, 2007.
  2. Kogge, Peter M. and Jay B. Brockman, "Redundancy in Multi-core Memory-rich Application-Specific PIM Chips," International Workshop on Innovative Architectures (IWIA'06), Kohala Coast, HI, Jan. 23-25, 2006
  3. Timothy J. Dysart, Kogge, Peter M., Craig S. Lent, and Mo Liu. "An Analysis of Missing Cell Defects in Quantum-Dot Cellular Automata." IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale  Architectures (NANOARCH '05) in conjunction with the VLSI Test Symposium.Palm Springs, CA. May 1, 2005. pp.3.1-3.7
  4. Kogge, Peter M., "An Exploration of the Technology Space for Multi-core Memory/Logic Chips for Highly Scalable Parallel Systems," International Workshop on Innovative Architectures (IWIA'05), Turtle Bay, HI., Jan. 18-19, 2005.
  5. Kogge, Peter M., "Architectures and Execution Models: How New Technologies May Affect How Languages Play on Future HPC Systems," Keynote talk, 17th Int. Workshop on Languages and Compilers for Parallel Computing (LCPC04), West Lafayette, IN, Sept. 23, 2004.
  6. Jay B. Brockman, Kogge, Peter M., S. Thoziyoor, S. Kuntz. "A Low Cost Multithreaded Processing-In-Memory System," 3rd Workshop on Memory Performance Issues (WMPI-2004), ISCA, Munich, Germany, June, 2004.
  7. Sterling, Thomas and Kogge, Peter M.. "Custom-Enabled System Architectures for High End Computing," International Workshop on Innovative Architectures (IWIA'04), Maui, HI., Jan. 12-13, 2004.
  8. Kogge, Peter M., "Of Piglets and Threadlets: Architectures for Self-Contained, Mobile, Memory Programming," International Workshop on Innovative Architectures (IWIA'04), Maui, HI., Jan. 12-13, 2004.
  9. Kogge, Peter M., Arun Rodriguez, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian, "A Comparative Analysis of Power and Energy Management Techniques in Real Embedded Applications, 6th International Workshop on Innovative Architectures (IWIA'03), Kauai, HI, Jan. 27-29, 2003.
  10. Robert J. Minerick, Vincent W. Freeh, and Kogge, Peter M., "Dynamic power management using feedback." Proc. of Workshop on Compilers and Operating Systems for Low Power, pp. 6-1 to 6-10, Charlottesville, Va, September, 2002.
  11. Sarah Elizabeth Frost, Arun F. Rodrigues, Andrew W. Janiszewski, Randal T. Rausch, and Kogge, Peter M. "Memory in Motion: A Study of Storage Structures in QCA." 1st Workshop on Non-Silicon Computation (NSC-1), held in conjunction with 8th Int. Symp. on High Performance Computer Architecture (HPCA-8), Boston, MS. Feb. 3, 2002.
  12. Michael T. Niemier, Arun F. Rodrigues, and Kogge, Peter M. "A Potentially Implementable FPGA for Quantum Dot Cellular Automata," , 1st Workshop on Non-Silicon Computation (NSC-1), held in conjunction with 8th Int. Symp. on High Performance Computer Architecture (HPCA-8), Boston, MS. Feb. 3, 2002.
  13. Murphy, Richard and Kogge, Peter M.. "Trading Bandwidth for Latency: Managing Continuations through a Carpet Bag Cache," Int. Workshop on Innovative Arch., Kona, HI, Jan. 12-13, 2002.
  14. Zawodny, Jason and Kogge, Peter M., "Cache In Memory," International Workshop on Innovative Architecture 2001 (IWIA01), Maui High Performance Computer Center, Maui, HI, Jan. 18-19, 2001.
  15. Kogge, Peter M., Vincent W. Freeh, Kanad Ghose, Nikzad Toomarian, Nazeeh Aranki, "Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
  16. Ghose, Kanad, Dmitry Ponomarev, Gurhan Kuck, Andrew Flinders, Kogge, Peter M., "Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
  17. Kogge, Peter M., "PIM Architectures to Support Petaflops Level Computation in the HTMT Machine," 3rd Int. Workshop on Innovative Architectures, Maui High Performance Computer Center, Maui, HI, Nov. 1-3, 1999.
  18. Niemier, M.T. and Kogge, P.M. "Designing a Microprocessor Using Quantum Cellular Automata (QCA)," 6th MEL-ARI Review, Duisburg, Germany, July 1999.
  19. Kogge, Peter M., "In Pursuit of a Petaflop: Overcoming the Bandwidth/Latency Wall," 10th Annual Workshop on Interconnections within High-Speed Digital Systems, 9-12 May 1999, Hilton of Santa Fe, Santa Fe, NM
  20. Niemier, Michael and Kogge, Peter M., "Logic in Wire: Using Quantum Dots to implement Really Dense Logic," Proc. Third Petaflop Workshop, associated with Frontiers of Massively Parallel Processing, Annapolis, MD, Feb. 22, 1999.
  21. Kogge, Peter M., "Processors-In-Memory (PIM) Chip Architectures for Peta(FL)ops Computing," Peta(FL)ops Workshop as part of 1995 Frontiers in Computing, Va., Feb. 6, 1995.
  22. Kogge, Peter M., "Avionics, AI, and Embedded Processing Systems," AIAA Computers in Aerospace VI, Boston, MA, Oct. 7, pp. 236-245, 1987
  23. Kogge, Peter M., "The FSD Owego Artificial Intelligence Laboratory," IBM FSD Technical Directions, Vol. 12, No. 3 and 4, pp. 13-16, 1986
  24. Kogge, Peter M., "High Performance Inference Processing," IBM FSD Technical Directions, Vol. 12, No 3 and 4, pp. 17-21, 1986
  25. Kogge, Peter M., "Advanced Processing System," IBM FSD Technical Symp., Rockville, MD, Sept. 1984
  26. Kogge, Peter M., "Standard ISAs and VLSI - Two Interacting Trends," 2nd AFSC Standardization Conf., Dayton, OH, Nov. 29, 1982
  27. Kogge, Peter M. and P. Olsen, "The Army's MIL-STD-1862 and the Military Computer Family," IBM FSD Technical Directions, Vol. 7, No. 2, Summer, 1981

Tutorials

  1. Kogge, Peter M., "The International Technology Roadmap for Semiconductors and Its Effect on n Scalable High End Computing," Tutorial, Supercomputing, Tampa, FL, Nov. 2006.
  2. Kogge, Peter M., Erik DeBenetictis and David Keyes, "Issues for the Future of Supercomputing: Impact of Moore's Law and Architecture on Application Performance," Tutorial M09, Supercomputing'05, Seattle, WA, Nov. 14, 2005
  3. Kogge, Peter M. Seminar series on "Declarative Computing: A Different Path to Harnessing the Power of Parallelism," 1st School of High Performance Scientific Computation, Rio de Janeiro, Brazil, Aug. 1992, also AIAA Aerospace Sciences Conf., Reno, NV, Jan. 1994
  4. Kogge, Peter M. and K. Ghose, Tutorial on "Pipelining and Fine Grain Parallelism," 21st Int. Conf, on Parallel Processing, Chicago, IL, Aug. 1992
  5. Kogge, Peter M. and K. Ghose, Tutorial on "Pipelining: Parallelism in the Small," 19th Int. Symp. on Computer Arch., Gold Coast, Australia, May 1992
  6. Kogge, Peter M., Tutorial on "Declarative Computing," 19th Int. Symp. on Computer Arch., Gold Coast, Australia, May 1992

Other Talks

  1. IEEE podcast on Exascale computing report, Dec. 2008
  2. S.E. Frost-Murphy, E.P. DeBenedictis, P.M. Kogge, "Using Nanotechnology to Solve Hard Problems Better", CRA-W/CDC Computer Architecture Workshop, Princeton, NJ, July 19-21, 2006.  Poster.
  3. Kogge, Peter M., "Light Weight State & PIM: Enabling New HEC Architectures," Presentation to High End Computing Revitalization Task Force (HECRTF), Sheraton Hotel, Washington D.C., June 17-18,2003.
  4. Kogge, Peter M., "State: the High End's Undiscovered Country," White Paper for High End Computing Revitalization Task Force (HECRTF), Sheraton Hotel, Washington D.C., June 17-18,2003.
  5. Michael G. Kirkpatrick Vincent W. Freeh Kogge, Peter M. Robert J. Minerick, "Exploiting Morphable Microarchitectures for Saving Energy," Univ. of Notre Dame CSE Dept. Tech. Report, 0109, Aug. 22, 2001.
  6. Niemier, Michael, and Kogge, Peter M., "Quantum Cellular Automata," Nanotech 2000, Dallas, TX, Sept. 27, 2000
  7. Guest on Milton Friedman Show on WGN Radio, Chicago, on 4/29/00, on topic of nanotechnology.
  8. Kogge, Peter M., "Redefining Memory," Stanford University, Nov. 16, 1998.
  9. Kogge, Peter M., Jay B. Brockman, Robert Ferraro, Eric Mjolsness, Paul S. Kapcio, Joseph R. Marshall, "Use of Processing-In-Memory (PIM) Technology to Enable On-Site "Geologist's Assistant" Processing," NASA JPL Mars Micromission Workshop, Pasadena, CA, May 21-22, 1998, pp.44-45.
  10. Kogge, Peter M., "Processing In Memory: A Technology for Scalable Computing," Invited talk, NSF Workshop on 500 Million Transistor Chips, Princeton University, Princeton, NJ., March 11-12, 1998.
  11. Kogge, Peter M., Jay B. Brockman, Thomas Sterling, and Guang Gao, " Processing-In-Memory: Chips to Petaflops," IRAM Workshop, Int. Symp. on Computer Arch., Denver, CO, June 1, 1997, paper and presentation.
  12. Kogge, Peter M., and Jay B. Brockman, "Processing-In-Memory (PIM): Capabilities and Opportunities for Deep Space Systems," CISM Workshop on X2000 Deep Space Processing, JPL, Pasadena, CA, June 3, 1997.
  13. Kogge, Peter M., Jay B. Brockman, Vincent Freeh, Steven C. Bass, "Petaflops, Algorithms, and PIMs," 1997 Petaflops Algorithm Workshop (PAL'97), Williamsburg, VA, April 13-18, 1997, paper and presentation.
  14. Kogge, Peter M. invited panelist Petaflops Computing session, topic: "PIMs and Petaflops", 1996 Supercomputing Conf., Nov. 22, 1996, Pittsburgh, PA
  15. Kogge, Peter M., "Procesor-In-Memory Based Architectures for Very High Performance MPP Computing," invited talk IBM Workshop on Performance Analysis and its Impact on Design, on opening of IBM VLSI Research Lab, Austin, TX, March 27, 1996, also Univ. of California, Berkeley, ECE Dept., April 8, 1996
  16. Kogge, Peter M., "Processor-In-Memory Based Architectures for Petaflops MPP Computing," 1995 NSF-NASA Workshop on Petaflops Applications, Bodega Bay, CA, Aug. 18-22, 1995, also NEC Reseach Labs, Princeton, NJ, Oct. 1995
  17. Invited Participant, NASA/JPL Workshop on Microspacecraft, Feb. 1995
  18. Kogge, Peter M., "Computing Post 2007 - the Peta(Fl)ops Challenge," IBM T.J. Watson Research Center, Feb. 7, 1995. Also to Purdue Univ. ECE Dept., Jan. 31, 1995.
  19. Kogge, Peter M., " Peta(Fl)ops Computer Architectures," JASON Group, San Diego, CA, June 1994
  20. Invited Participant, Caltech Workshop on Peta(fl)op Processing, Pasadena, CA Feb., 1994
  21. Kogge, Peter M., "The EXECUBE Approach to Massively Parallel Processing," Distinguished. Lecturer Talk, Univ. of Southern Ca., Sept. 1993, also Univ. of Washington, Sept. 1993, also Univ. of Notre Dame, Oct. 1993, also Univ. of Utah, Jan. 1994, also Binghamton Univ., Feb. 1994.
  22. Kogge, Peter M. ., "EXECUBE and Synthetic Aperture Radar," JASON Group, San Diego, June 1993.
  23. Kogge, Peter M., "An Introduction to AI," AIAA Aerospace Conf., Reno, NV, Jan. 1993
  24. Kogge, Peter M., "Declarative Computing: A Technology Driver," Opening Address for 1992 German National Computer Conference, Kiel, Germany, March 1992.
  25. Kogge, Peter M., "Content Addressable Memories," NAECON, Dayton OH, May 1991, also Univ. of Notre Dame, Sept. 1991, also Univ. of Utah, Oct. 1989
  26. Kogge, Peter M., "AI Programming Paradigms," USAF STSC Joint Software Conference, Salt Lake City, Utah, April 1991
  27. Kogge, Peter M., M. Robinson, T. Giambra, "Distributed Intelligent Defensive System," AIAA Aerospace Conf., Jan 1989, also DARPA Workshop on Requirements for Real Time Avionics Processors for Artificial Intelligence, Monterey, CA, Sept. 1989
  28. Kogge, Peter M. IEEE Distinguished Lecturer Series, "Compiling Parallel Logic Programs," and "Functional Languages and Parallelism," IEEE Society of Orlando, Orlando, FL, Jan. 1990, also Univ. of South Florida, Orlando, FL, Jan. 1990, also Univ. of Southwest Louisiana, Lafayette, LA, Jan. 1989, also Georgia Tech., Atlanta, GA, Jan. 1989, also Iowa State Univ., Ames, IA, March 1988, also Cornell Univ., Ithaca, NY, Feb. 1988
  29. Kogge, Peter M., "VLSI and Rules Based Systems, " 1988 International Workshop on VLSI for AI, Oxford, England, July 1988, also IBM ITL on Expert Systems, Yorktown Heights, NY Oct. 1988, also Technical Vitality Series Talk, IBM Rochester, Dec. 1988
  30. Kogge, Peter M., "AI and Scientific Computing: Are They Compatible?," Panel Session at Int. Session on Computer Arch., Tokyo, Japan, May, 1986
  31. Kogge, Peter M., "Artificial Intelligence," Guthrie Medical Center, Guthrie, PA, Feb. 1986
  32. Kogge, Peter M., "How Inference Engines Really Work," IBM FSD Conf. on AI, Gaithersburg, MD, June 1985, also ARTWG meeting, Ft. Worth, TX, Oct. 1986, also SUNY Binghamton CS Lecture Series, March 1987
  33. Kogge, Peter M., "Function Based Computing and Parallelism," SHARE European Group Spring Meeting, Eindoven, Netherlands, April, 1985
  34. Kogge, Peter M., "Pipelined Processing," New York Univ., May 1984, also IBM Europe Institute, Davos, Switzerland, July, 1984, also AIAA von Neumann Computer Workshop, Nassau, TX, Oct. 1984
  35. Kogge, Peter M., "Functional Languages and Parallelism," IBM Europe Institute, Davos, Switzerland, July, 1984
  36. Kogge, Peter M., "Timing, Control, and Performance - Scheduling Activities on a Pipeline," MIT, Cambridge, MA, April, 1982
  37. Kogge, Peter M., "Development Methodology for Pipelined Algorithms," IBM Symp. on Math and Computation, Watson Research Center, Yorktown Heights, NY, Sept., 1976