What engineering is, what an engineering major is all about, what is important in teaching an introductory engineering course, and why textbook salespeople shouldn't fear engineering professors---all in 3 minutes. Presented at the John Wiley & Sons annual sales meeting, January 2008 |
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The following lectures were presented using materials from Jay Brockman's Introduction to Engineering textbook in his sophomore-level Digital Logic Design course during 2007-08.
| Chapter |
Topic |
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| 2 |
Concept Maps |
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| 3 |
What Do You Know: Levels of Understanding |
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| 3 |
Class Exercise: Levels of Understanding |
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| 3 |
A Framework for Problem Solving |
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| 3 |
How Much Carbon Dioxide Does a Typical Passenger Car Produce |
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| 3 |
Getting Unstuck: Heuristics |
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| 3 |
Class Exercise: Formulating Plans |
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A complete set of lecture videos recorded by Jay Brockman based on Frank Vahid's Digital Design textbook and PowerPoint slides are availble for free for instructors using this book. See the Wiley textbook companion site for details
These tutorials were developed for CSE 221, Digital Logic Design at Notre Dame, 2007-08.
| Introduction to Schematic Capture and Simulation |
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| Design and Simulation of Flip-Flops and Latches |
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| Using Busses |
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| Controller Design Part 1: State Registers |
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| Controller Design Part 2: Combinational Logic and Simulation |
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| Creating a Testbench Waveform with Multiple Clocks |
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| Downloading from Xilinx ISE to the Digilent Basys Board (USB Version) |
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| Downloading from Xilinx ISE to the Digilent Basys Board (JTAG Version) |
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| Interfacing to LEDs, Seven Segment Displays, and Keyboards |
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| Verilog Design Flow Part 1: Design and Simulation |
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| Verilog Design Flow Part 2: Synthesis, Implementation, and Downloading to Basys |
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| Mixed Verilog and Schematic Design Part 1: Design and Simulation |
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| Mixed Verilog and Schematic Design Part 2: Synthesis |
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| Generation and Simulation of Xilinx Memory Cores |
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These lectures were developed for CSE 221, Digital Logic Design at Notre Dame, 2007-08.
| Introduction to Combinational Logic in Verilog |
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| Schematics vs. Structural Verilog using Xilinx ISE |
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| Combinational Logic: Introduction to Structural and Behavioral Verilog Models |
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| Blocking and Non-Block Signal Assignment in Verilog |
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| Designing Finite State Machines with Verilog |
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These lectures were developed during the Fall semester of 2008 for CSE/EE 462, VLSI Design. The lectures are based on the slides developed by David Harris of Harvey Mudd College, for CMOS VLSI Design, A Systems and Circuits Perspective, Third Edition, by David Harris and Neil Weste, Addison-Wesley. I just switched to the book this year--plan on finishing the video lectures and fixing up the course web site next year!
| Course Introduction |
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| The MOS Switch |
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| Fabrication and Layout |
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| History and Trends |
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| Complementary CMOS and Transmission Gate Logic |
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| Latches and Flip-Flops |
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| Layout and Stick Diagrams |
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| A Simplified MIPS Processor |
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| Ideal MOSFET I-V Relationships (Part 1) |
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| Ideal MOSFET I-V Relationships (Part 2) |
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| Non-Ideal MOSFET I-V Relationships |
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