Synthesizing Verilog to the AMI05 Technology Using Leonardo

1. Log into athena.cse.nd.edu

ssh -X athena.cse.nd.edu

2. Set up the Mentor Graphics environment

source /home/mentor/.bstrc

3. Go to your working directory and copy this Verilog file with a 4-bit ripple-carry adder to it:  ripple_tut.v
4. Invoke leonardo

setenv MGC_WD .

leonardo &

Click OK in the popup to get a license LeonardoSpectrum level 3

5. Select Tools->Flow Tabs from main menu
6. Load the AMI05 technology library by typing the following into the Leonardo command window. (Window in bottom right corner with extremely small font.)

load_lib /home/mentor/adk3_0/technology/leonardo/ami05_typ

7. Go to the Input flow tab.  Click the Open File button and open ripple_tut.v.  Highlight the file in the list window and click the Read button.
8. Go to the Optimize flow tab. 
• Make sure Technology is blank to use the default technology (AMI05, not an FPGA). 
• Make sure ripple4->INTERFACE is highlighted in the design list.
• Select Preserve Hierarchy.
• Click the Optimize button.

After optimization, a new design INTERFACE_XRTL should appear in the design list.

9. Open the schematic for the synthesized design mapped to the AMI05 library by double-clicking on ripple4->INTERFACE.  It should contain full adder (fadd) blocks.  Double-click one of these to view the schematic for that.  (Note that INTERFACE_XRTL is the technology-independent RTL design.  You can also look at the schematic for this).
10. Go to the Output flow tab.  Set the output file type as Verilog, and save the output as ripple_tut_ami05.v
11. You can experiment with different synthesis optimization options, such as optimize for timing instead of area, or flattening the hierarchy, or mapping to an FPGA technology.  Note that if you want to restore hierarchy after you've flattened it, you need to go back to the Input tab and re-read the Verilog file.
12. Close Leonardo and log out of athena when you're done.

Generating a Mentor Graphics EDDM Design Viewpoint for Layout

1. Back on a Linux box, set the Mentor environment for ICStation

source /opt/und/mentor/.icflowrc

2. Set the working directory to where your synthesized Verilog file is and invoke DesignArchitectect_IC

setenv MGC_WD .

da_ic &

3. From the main menu, select File->Import Verilog.  In the popup, click on Netlist File(s) to get another popup and fill it in as follows, using the file browser buttons and Add-> buttons:
• Netlist File(s): ripple_tut_ami05.v
• Output Directory: $MGC_WD
• Map File: adk_map.vmp

Click OK on both popup windows

4. To view the schematic, select File->Open-Schematic from the main menu and browse to the ripple4 component.
5. Exit da_ic by selecting MGC->Exit from the main menu.
6. Back at the Linux prompt, list your working directory.  You should see new directories that correspond to the EDDM components for ripple4 and fadd (as well as some other files).
7. Create design viewpoints from the EDDM component that you just created by typing:

adk_dve ripple4

Using ICStation for Automatic Placement and Routing

1. Open ICStation by typing at the Linux prompt

adk_ic &

2. Click on the Create button in the panel (on the right of the window) to create a new layout cell.  Fill in the popup as follows:
• Cell Name: ripple4
• Attach Library: $ADK/technology/ic/process/ami05
• Process: $ADK/technology/ic/process/ami05
• Rules File: $ADK/technology/ic/process/ami05.rules
• Angle Mode: 45
• Cell Type: Block
• Connectivity?: With connectivity
• EDDM Schematic Viewpoint: ripple4/layout
• Logic Loading Options: Flat

Click okay and don't worry about the warnings about read locks, etc.

3. In the IC Palette, click the ADK Edit button at the bottom to switch to the ADK Edit palette.  In the ADK Edit palette, click on the P&R button to get the Place and Route Palette.
4. Floorplan the design by clicking on the Autofp button.  Use the default values in the popup and click the OK button.  Some green bounding bars and boxes should appear in the cell.
5. Place the cells in the design by clicking the StdCel button under the Auto Place heading in the palette and click OK in the popup.  You should see the cell placed in rows with yellow lines called "overflows" showing the connections between them.
6. Place the ports by clicking the Ports button.  Accept default values (you might do otherwise later) and click OK.
7. Now it's time to route the nets in metal.  VERY IMPORTANT: there is a bug in the ADK cell library that can cause the router to short metal lines together when it tries to route wires over the cells.  To avoid this, we'll need to restrict the router to only using metal 2 over the cells!!!!
8. Click the Auto Route -> All button on the palette, then click on Options in the popup, then click on OCR Options (over cell routing) in that popup.  Here's the key step to saving you hours of debugging looking for shorts in your design:
• Delete the 3 and the 1 from the Routing Levels boxes so that only routing level 2 remains
• then click OK in each of the popups
9. Most (maybe all) of the nets should be routed at this point, but some overflows (yellow lines) might remain.  You'll need to be very careful routing overflows that go horizontally across cells to make sure that they don't cause shorts!!! To route them:
• Select and overflow and click Auto Route -> PtToPt
• In the popup, click on the Preferred Route button and draw a rough path of line segments (clicking at each corner) that routes a path vertically over the cell to a channel, horizontally across the channel, and then vertically back down.  Double click to finish.  Make sure that the resulting path only has vertical metal 2.  Repeat for each "difficult" overflow.
• You can route the remaining "easy" overflows that don't go over cells automatically.  Type "check over" with the mouse pointer on top of the cell window.  A popup will appear as soon as you start typing. Then hit return and you'll get another popup.  Click on OK.
• All overflows in the layout should now be highlighted.  Click Auto Route -> OvrFlw in the palette.
• Using the left mouse button, drag a box around the entire cell.  The overflows should now be routed.

Layout versus Schematic Check

1. Still in ICStation we need to perform a layout versus schematic check to verify that the layout is actually a correctly placed-and-routed version of your netlist.
2. Go back to the ADK Edit palette.  Near the bottom, click on the LVS button.  Fill in the popup with the following:
• Source Name: ripple4/lvs
• Source Type: eddm

Click OK

3. In the ADK Edit palette, click on the little triangular arrow next to Report (next to the LVS button) and select LVS from the popup.
4. Look at the report that comes up.  Scroll down and you should see a smiley face (really!!) and a check mark if all is well.  If not:
• If the top of the report indicates a short, you either didn't restrict OCR routing to level 2 metal, or made a mistake with the routing of overflows.  Go back to the Route All step and start routing again.
• If you get an error message for different number of nets, there are either still overflows in the cell, or you might have accidentally deleted and overflow and never routed it.  Go back to the Route All step and begin again.

Viewing the Insides of Cells

1. With click and drag the mouse over the entire cell to select everything.
2. From the main menu, select Context -> Hierarchy -> Peek.  In the popup, for number of levels enter at least 2.
3. To turn the display of layers on and off, you need the Layer Palette.  To get it, from the main menu select Other -> Layers -> Show Layer Palette.  In the popup, enter the following into the layers dialog box before clicking OK:

2,3,41-51,61,62

4. Clicking the middle mouse button on a layer in the palette will turn it's display on and off.