HSPICE Tutorial

Introduction

HSPICE is Synopsys' version of SPICE, the industry-standard circuit simulator. In this tutorial, you will follow the steps to simulate a CMOS inverter using the AMI 0.5 micron process design rules, and then try simulating a NAND gate on your own. Please refer to the online HSPICE and AvanWaves documentation for clarification as needed.

Setting Up Your Environment

source /usr/local/src/hspice/v2001.4/2001.4/bin/cshrc.meta

You should put this statement into your .cshrc file so that you don't need enter it for each hspice session.

Running a Transient Analysis

Editing the Input File

Spice files contain a number of sections:

title line
comments
netlist declaration
subcircuit definitions
device model definitions
stimuli
simulation control commands
simulation output format commands

Using your favorite text editor, type in the following lines and save the file in your hspice_tut directory as inv_transient.sp

A copy of the file can also be found here.

Note: hspice seems to require that there are no leading blank spaces on each line of the input file. Beware of this if you cut-and-paste!


Inverter Transient Analysis (this is the title line)

* enable post-processing by AvanWaves
.options post

* device model file
.include ami05.md

* transient analysis: step size = 50 psec, duration = 2 nsec
.tran 50p 2n

* specify nodes to print (hspice will print them all, anyway)
.print tran v(in) v(out)

* here's the inverter netlist declaration
* mosfet: mxx drain gate source substrate model length width
m1 OUT IN VDD VDD CMOSP l=.5u w=2u
m2 OUT IN GND GND CMOSN l=.5u w=2u

* here's the load capacitor on the inverter output
* capacitor: cxx node1 node2 capacitance
cload OUT GND 100f

* constant voltage source: vxx node1 node2 voltage
VDD VDD GND 5

* pulsed voltage source:
* vxx node1 node2 PULSE params
* params = vlow vhigh delay rise fall pulse_width period
VIN IN GND PULSE 0 5 .5n .1n .1n .5n 2n

.end


Running HSPICE

Viewing Results of Transient Analysis in AvanWaves

Generating a Voltage Transfer Characteristic (Vout vs. Vin Plot)

To obtain a voltage transfer characteristic for a circuit, we run a DC parameter sweep in HSPICE.  This is done with a command of the form:

.DC <voltage source> <start voltage> <end voltage> <increment>

The file inv_vtc.sp contains an example and is also listed below.  Run HSPICE on this file as above.


Inverter Voltage Transfer Characteristic

* enable post-processing by AvanWaves

.options post

* device model file
.include ami05.md

* here's the inverter netlist declaration
* mosfet: mxx drain gate source substrate model length width
m1 OUT IN VDD VDD CMOSP l=.5u w=2u
m2 OUT IN GND GND CMOSN l=.5u w=2u

* constant voltage source: vxx node1 node2 voltage
VDD VDD GND 5

* Define a voltage source connected to Vin and initialize voltage to 0
Vin IN Gnd 0

* Sweep Vin from 0 to 5 volts in increments of .1 volt
.DC Vin 0 5 .1

* Print the voltage at OUT
.print dc v(OUT)

.end


Viewing Voltage Transfer Characteristic in AvanWaves

Generating MOSFET IV Characteristics

To get IV characteristics for a MOSFET, we need to run a nested DC voltage sweep, that varies the drain voltage in the inner loop and the gate voltage in the outer loop.  The HSPICE input file nmos_iv.sp provides an example of generating IV characteristics for an NMOS device.   The file is also listed below:



NMOS IV Characteristics

.options post
.include ami05.md

* There's only a single MOSFET in the netlist
m1 drain gate Gnd Gnd CMOSN l=0.5u w=2u

* Voltage sources on the gate and drain initially set to 0
Vgate gate Gnd 0
Vdrain drain Gnd 0

* perform a nested voltage sweep
* inner sweep: Vdrain from 0 to 5 by .1
* outer sweep: Vgate from 0 to 5 by 1

.DC Vdrain 0 5 .1 Vgate 0 5 1

* printing MOS currents: I1-drain, I2-gate, I3-source
.print dc I1(m1)

.end


Viewing IV Characteristics in AvanWaves