This course teaches the fundamental principles of CMOS digital integrated circuit (IC) design. The course makes extensive use of modern CAD tools for IC layout and simulation.
Professor:
Dr. Jay Brockman
323B Cushing Hall
574 631-8810
jbb@cse.nd.eduDr. Mike Ciletti
ciletti@eas.uccs.edu
Graduate Assistant:
Daniel Rinzler, CSE
222 Cushing Hall
634-8854
drinzler@nd.eduTanvir Alam, EE
227 Cushing Hall
634-5644
malam1@nd.edu
MWF 12:50-1:40
DeBartolo 120
Rabaey, Chandrakasan, and Nikolic. Digital Integrated Circuits, 2nd Edition. Prentice Hall 2003.
| Midterm Exam | 25% |
| Final Exam | 25% |
| Project | 25% |
| Homework | 20% |
| Participation | 5% |
| Date | Lecture or Topic | Reading | Assignment |
| Wed Aug 23 | Introduction and VLSI Design Overview | ||
| Fri Aug 25 | Introduction and VLSI Design Overview | CMOS Logic and Layout | |
| Mon Aug 28 | CMOS Logic and Layout | ||
| Wed Aug 30 | Technology Trends | ||
| Fri Aug 31 | HDL-Based VLSI Design Methodology-1 | Verilog Simulation | |
| Mon Sep 4 | HDL-Based VLSI Design Methodology-1 | ||
| Wed Sep 6 | Verilog Simulation with Modelsim | ||
| Fri Sep 8 | HDL-Based VLSI Design Methodology-2 | Verilog Synthesis | |
| Mon Sep 11 | HDL-Based VLSI Design Methodology-2 | ||
| Wed Sep 13 | HDL-Based VLSI Design Methodology-2 | Synthesis with Mentor Graphics Precision | |
| Fri Sep 15 | HDL-Based VLSI Design Methodology-3 | System Design | |
| Mon Sep 18 | HDL-Based VLSI Design Methodology-3 | ||
| Wed Sep 20 | Adders and Multipliers | ||
| Fri Sep 22 | Adders and Multipliers | Project Proposal and Adder Design | |
| Mon Sep 25 | Fabrication Process | ||
| Wed Sep 27 | Leonardo and ICStation Tutorial (in Fitzpatrick cluster) | ||
| Fri Sep 29 | Project Discussion | ||
| Mon Oct 2 | Switching Delay Model | Adder Synthesis and Layout | |
| Wed Oct 4 | Switching Delay Model | ||
| Fri Oct 6 | Review for Midterm | ||
| Mon Oct 9 | Midterm Exam | ||
| Wed Oct 11 | Nanosim Tutorial (6:30-8:00, Fitz cluster) | ||
| Fri Oct 13 | No Class (sign-up for meeting either Tu-Th instead) | ||
| Mon Oct 23 | Go over exam, Switching Delay Model | ||
| Wed Oct 25 | Switching Delay Model | ||
| Fri Oct 27 | Design for Speed | ||
| Mon Oct 30 | Design for Speed | Circuit Delay | |
| Wed Nov 1 | Project meetings to discuss test plan (no lecture) | ||
| Fri Nov 3 | Design for Speed | ||
| Mon Nov 6 | MOS Transistor Model | ||
| Wed Nov 8 | Project Meetings | ||
| Fri Nov 10 | MOS Transistor Model | ||
| Mon Nov 13 | Static View of CMOS Inverter | ||
| Wed Nov 15 | |||
| Fri Nov 17 | Complete Verilog Design/Simulation/Synthesis | ||
| Mon Nov 20 | |||
| Wed Nov 22 | |||
| Fri Nov 24 | No class, Thanksgiving | ||
| Mon Nov 27 | |||
| Wed Nov 29 | |||
| Fri Dec 1 | |||
| Mon Dec 4 | Project Presentations | ||
| Wed Dec 6 | Project Presentations |